{
  "participants": [
    {
      "name": "Michael Nolan",
      "email": "mtnolan2640@gmail.com"
    },
    {
      "name": "RED Semiconductor Ltd",
      "email": "lkcl@libre-soc.org"
    },
    {
      "name": "Jacob R. Lifshay",
      "email": "programmerjake@gmail.com"
    },
    {
      "name": "Luke Kenneth Casson Leighton",
      "email": "lkcl@lkcl.net"
    },
    {
      "name": "Cesar Strauss",
      "email": "cestrauss@gmail.com"
    },
    {
      "name": "Dmitry Selyutin",
      "email": "ghostmansd@gmail.com"
    },
    {
      "name": "R Veera Kumar",
      "email": "veerakumar.r@gmail.com"
    },
    {
      "name": "Dan Leighton",
      "email": "danleighton@gmail.com"
    }
  ],
  "preamble": "",
  "type": "Group",
  "url": "https://bugs.libre-soc.org/show_bug.cgi?id=158",
  "plan": {
    "intro": [
      ""
    ],
    "tasks": [
      {
        "title": "194 A nmigen-based RISC-V Formal correctness proof suite is needed",
        "intro": [
          "https://bugs.libre-soc.org/show_bug.cgi?id=194\n "
        ],
        "amount": 0,
        "url": "{{ https://bugs.libre-soc.org/show_bug.cgi?id=194 }} ",
        "milestones": []
      },
      {
        "title": "195 Formal correctness framework is needed for Power ISA",
        "intro": [
          "https://bugs.libre-soc.org/show_bug.cgi?id=195\n "
        ],
        "amount": 12000,
        "url": "{{ https://bugs.libre-soc.org/show_bug.cgi?id=195 }} ",
        "milestones": [
          {
            "description": "306 Formal Correctness Proof for ALU pipeline",
            "amount": 500
          },
          {
            "description": "331 Formal Correctness Proof for LOGICAL pipeline",
            "amount": 400
          },
          {
            "description": "332 Formal correctness proof needed for CR pipeline",
            "amount": 300
          },
          {
            "description": "335 Formal Correctness Proof for Branch pipeline",
            "amount": 400
          },
          {
            "description": "340 formal proof of POWER9 SHIFTROT pipeline needed",
            "amount": 2400
          },
          {
            "description": "418 SPR pipeline formal correctness proof needed",
            "amount": 400
          },
          {
            "description": "419 MUL pipeline formal proof needed",
            "amount": 550
          },
          {
            "description": "421 TRAP pipeline formal correctness proof needed",
            "amount": 500
          },
          {
            "description": "wrapup",
            "amount": 6550
          }
        ]
      },
      {
        "title": "196 Formal correctness proof needed for the IEEE754 FPU",
        "intro": [
          "https://bugs.libre-soc.org/show_bug.cgi?id=196\n "
        ],
        "amount": 12000,
        "url": "{{ https://bugs.libre-soc.org/show_bug.cgi?id=196 }} ",
        "milestones": [
          {
            "description": "162 Formally Verify the FSGNJ module",
            "amount": 150
          },
          {
            "description": "163 Formally Verify the FPMAX module",
            "amount": 150
          },
          {
            "description": "165 Formally verify the FPCMP (FEQ, FLE, FLT) module",
            "amount": 150
          },
          {
            "description": "565 Improve formal verification on PartitionedSignal",
            "amount": 3000
          },
          {
            "description": "835 add support for smtlib2 floating-point to yosys and nmigen",
            "amount": 2600
          },
          {
            "description": "883 add cvc5 and bitwuzla to hdl-yosys-tools\n(Sub-sub-task of 835)",
            "amount": 800
          },
          {
            "description": "869 Formal verification of fadd for just round-nearest-ties-to-even without exception flags/traps",
            "amount": 1500
          },
          {
            "description": "874 Implementation and Formal verification of fadd for all rounding modes but without exception flags/traps",
            "amount": 1500
          },
          {
            "description": "876 Implement and Add Formal Proof for fsub in the fpadd pipeline",
            "amount": 500
          },
          {
            "description": "877 implementation and formal correctness proof for fp fused-mul-add pipeline excluding ieee754 exception flags",
            "amount": 1650
          }
        ]
      },
      {
        "title": "197 Formal correctness proof needed of the 6600-style Out-of-Order execution engine",
        "intro": [
          "https://bugs.libre-soc.org/show_bug.cgi?id=197\n "
        ],
        "amount": 5000,
        "url": "{{ https://bugs.libre-soc.org/show_bug.cgi?id=197 }} ",
        "milestones": [
          {
            "description": "342 formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed",
            "amount": 2500
          },
          {
            "description": "879 Formal proof of soc.experiment.compalu_multi.MultiCompUnit needed",
            "amount": 2500
          }
        ]
      },
      {
        "title": "198 Formal correctness proofs are needed for low-level libraries in LibreSOC",
        "intro": [
          "https://bugs.libre-soc.org/show_bug.cgi?id=198\n "
        ],
        "amount": 9000,
        "url": "{{ https://bugs.libre-soc.org/show_bug.cgi?id=198 }} ",
        "milestones": [
          {
            "description": "312 Formal Correctness Proof for CountZero needed (basically PriorityEncoder)",
            "amount": 150
          },
          {
            "description": "wrapup",
            "amount": 8850
          }
        ]
      },
      {
        "title": "577 gcc compiler, binutils and assembly macros for OpenPOWER-SV",
        "intro": [
          "https://bugs.libre-soc.org/show_bug.cgi?id=577\n "
        ],
        "amount": 12000,
        "url": "{{ https://bugs.libre-soc.org/show_bug.cgi?id=577 }} ",
        "milestones": [
          {
            "description": "833 svp64: generate code for integrating SVP64 concepts into binutils\n(Sub-sub-task of 550)",
            "amount": 1000
          },
          {
            "description": "838 sync or at least statically check fields.text, power_decoder, trans/svp64, CSVs between each other\n(Sub-sub-task of 550)",
            "amount": 1500
          },
          {
            "description": "844 binutils: implement the first revision with magic instruction\n(Sub-sub-task of 550)",
            "amount": 1300
          },
          {
            "description": "845 binutils: drop svmagic and deal with the prefix instead\n(Sub-sub-task of 550)",
            "amount": 1150
          },
          {
            "description": "849 binutils: parse macros in SVP64 and refactor code\n(Sub-sub-task of 550)",
            "amount": 2400
          },
          {
            "description": "867 add svindex instruction to binutils (and openpower-isa infrastructure)\n(Sub-sub-task of 550)",
            "amount": 1200
          },
          {
            "description": "578 python-based svp64 \"generator\" class",
            "amount": 500
          },
          {
            "description": "834 binutils: support draft fsins/fcoss/ternlogi instructions",
            "amount": 725
          },
          {
            "description": "847 dev-env-setup script for binutils-gdb for target powerpc64le-linux-gnu",
            "amount": 650
          },
          {
            "description": "857 binutils: provide tests for setvl/svstep/svshape/svremap",
            "amount": 650
          },
          {
            "description": "wrapup",
            "amount": 925
          }
        ]
      },
      {
        "title": "941 FOSDEM 2020 travel expenses",
        "intro": [
          "https://bugs.libre-soc.org/show_bug.cgi?id=941\n "
        ],
        "amount": 1460,
        "url": "{{ https://bugs.libre-soc.org/show_bug.cgi?id=941 }} ",
        "milestones": [
          {
            "description": "wrapup",
            "amount": 1460
          }
        ]
      }
    ],
    "rfp_secret": ""
  }
}