{
  "participants": [
    {
      "name": "Luke Kenneth Casson Leighton",
      "email": "lkcl@lkcl.net"
    },
    {
      "name": "Jacob R. Lifshay",
      "email": "programmerjake@gmail.com"
    },
    {
      "name": "Cole Poirier",
      "email": "colepoirier@gmail.com"
    },
    {
      "name": "whitequark",
      "email": "whitequark@whitequark.org"
    },
    {
      "name": "Cesar Strauss",
      "email": "cestrauss@gmail.com"
    },
    {
      "name": "R Veera Kumar",
      "email": "veerakumar.r@gmail.com"
    },
    {
      "name": "Dmitry Selyutin",
      "email": "ghostmansd@gmail.com"
    },
    {
      "name": "Maciej (3mdeb)",
      "email": "maciej.pijanowski@3mdeb.com"
    },
    {
      "name": "Andrey Miroshnikov",
      "email": "andy.miroshnikov@gmail.com"
    },
    {
      "name": "Tim Pearson",
      "email": "tpearson@raptorengineering.com"
    },
    {
      "name": "RED Semiconductor Ltd",
      "email": "lkcl@libre-soc.org"
    }
  ],
  "preamble": "",
  "type": "Group",
  "url": "https://bugs.libre-soc.org/show_bug.cgi?id=175",
  "plan": {
    "intro": [
      ""
    ],
    "tasks": [
      {
        "title": "244 Wishbone B4 Streaming Specification enhancement.",
        "intro": [
          "https://bugs.libre-soc.org/show_bug.cgi?id=244\n "
        ],
        "amount": 2500,
        "url": "{{ https://bugs.libre-soc.org/show_bug.cgi?id=244 }} ",
        "milestones": [
          {
            "description": "wrapup",
            "amount": 2500
          }
        ]
      },
      {
        "title": "245 Wisbone B4 Streaming Reference Implementations with unit tests",
        "intro": [
          "https://bugs.libre-soc.org/show_bug.cgi?id=245\n "
        ],
        "amount": 6500,
        "url": "{{ https://bugs.libre-soc.org/show_bug.cgi?id=245 }} ",
        "milestones": [
          {
            "description": "wrapup",
            "amount": 6500
          }
        ]
      },
      {
        "title": "246 Wishbone B4 Streaming I2S peripheral for LibreSOC",
        "intro": [
          "https://bugs.libre-soc.org/show_bug.cgi?id=246\n "
        ],
        "amount": 1350,
        "url": "{{ https://bugs.libre-soc.org/show_bug.cgi?id=246 }} ",
        "milestones": [
          {
            "description": "wrapup",
            "amount": 1350
          }
        ]
      },
      {
        "title": "248 Wishbone B4 Streaming presentation at ORConf 2020",
        "intro": [
          "https://bugs.libre-soc.org/show_bug.cgi?id=248\n "
        ],
        "amount": 650,
        "url": "{{ https://bugs.libre-soc.org/show_bug.cgi?id=248 }} ",
        "milestones": [
          {
            "description": "wrapup",
            "amount": 650
          }
        ]
      },
      {
        "title": "249 Additional Wishbone B4 peripherals for Libre-SOC (including conversion from patented AXI4)",
        "intro": [
          "https://bugs.libre-soc.org/show_bug.cgi?id=249\n "
        ],
        "amount": 12500,
        "url": "{{ https://bugs.libre-soc.org/show_bug.cgi?id=249 }} ",
        "milestones": [
          {
            "description": "468 wishbone downconverter needed",
            "amount": 200
          },
          {
            "description": "795 No console output from ls2 builds",
            "amount": 2000
          },
          {
            "description": "797 Add 10/100 OpenCores Ethernet MAC",
            "amount": 2300
          },
          {
            "description": "801 ls2/gram DDR3 controller not working on hardware",
            "amount": 6000
          },
          {
            "description": "806 Nest should be able to run at different clock rate than main CPU",
            "amount": 2000
          }
        ]
      },
      {
        "title": "250 Wishbone B4 Streaming Formal correctness proof needed",
        "intro": [
          "https://bugs.libre-soc.org/show_bug.cgi?id=250\n "
        ],
        "amount": 2500,
        "url": "{{ https://bugs.libre-soc.org/show_bug.cgi?id=250 }} ",
        "milestones": [
          {
            "description": "wrapup",
            "amount": 2500
          }
        ]
      },
      {
        "title": "362 improvements to nmigen and yosys",
        "intro": [
          "https://bugs.libre-soc.org/show_bug.cgi?id=362\n "
        ],
        "amount": 7000,
        "url": "{{ https://bugs.libre-soc.org/show_bug.cgi?id=362 }} ",
        "milestones": [
          {
            "description": "364 CXXRTL Python Interface",
            "amount": 4000
          },
          {
            "description": "458 PartitionedSignal needs nmigen constructs \"m.If\", Switch etc",
            "amount": 1250
          },
          {
            "description": "475 cxxsim improvements",
            "amount": 1750
          }
        ]
      },
      {
        "title": "383 Complete first functional POWER9 Core",
        "intro": [
          "https://bugs.libre-soc.org/show_bug.cgi?id=383\n "
        ],
        "amount": 10000,
        "url": "{{ https://bugs.libre-soc.org/show_bug.cgi?id=383 }} ",
        "milestones": [
          {
            "description": "186 Create decoder for SOC: Power ISA",
            "amount": 500
          },
          {
            "description": "305 Create Pipelined ALU similar to alu_hier.py",
            "amount": 400
          },
          {
            "description": "313 Create Branch Pipeline for POWER9",
            "amount": 250
          },
          {
            "description": "314 Create POWER9 Condition Register pipeline",
            "amount": 300
          },
          {
            "description": "323 create POWER9 MUL pipeline",
            "amount": 750
          },
          {
            "description": "324 create POWER DIV pipeline",
            "amount": 1500
          },
          {
            "description": "325 create POWER9 TRAP pipeline",
            "amount": 500
          },
          {
            "description": "330 create POWER9 Logic Pipeline",
            "amount": 300
          },
          {
            "description": "339 create POWER9 ROTATE (SHIFTROT) pipeline",
            "amount": 300
          },
          {
            "description": "344 missing mtmsr and mfsprd",
            "amount": 100
          },
          {
            "description": "345 define POWER9 regfiles",
            "amount": 200
          },
          {
            "description": "346 simplified test link between compunits and regfile",
            "amount": 750
          },
          {
            "description": "348 POWER9 SPR pipeline needed",
            "amount": 300
          },
          {
            "description": "349 privileged-instruction decoding function needed",
            "amount": 100
          },
          {
            "description": "351 create a \"block\" (mass) regfile port (read and write) onto an array-based regfile",
            "amount": 200
          },
          {
            "description": "382 nmigen wishbone Memory (SRAM) object needed",
            "amount": 150
          },
          {
            "description": "393 Hook up augmented-Wishbone Memory Bus to LDSTCompUnit (via PortInterface)",
            "amount": 300
          },
          {
            "description": "407 XICS interrupt controller is needed",
            "amount": 450
          },
          {
            "description": "409 deal with illegal instruction in simulator and hardware",
            "amount": 100
          },
          {
            "description": "414 debug port needed (JTAG, other frontend)",
            "amount": 250
          },
          {
            "description": "416 dec and tb POWER9 SPRs needed",
            "amount": 200
          },
          {
            "description": "426 LDST sign-extension support needed",
            "amount": 100
          },
          {
            "description": "427 LDST cache-inhibit instructions needed (l*cix,  st*cix)",
            "amount": 200
          },
          {
            "description": "435 PC and MSR need to be in the \"state\" (Decode2Execute1Type)",
            "amount": 100
          },
          {
            "description": "441 Avoid unit tests that depend on other unit tests being run first",
            "amount": 400
          },
          {
            "description": "471 bug in modsd  DIV FSM",
            "amount": 100
          },
          {
            "description": "476 addme ALU pipeline bug",
            "amount": 100
          },
          {
            "description": "477 add add instructions to power-instruction-analyzer",
            "amount": 250
          },
          {
            "description": "478 MFOCR and MCROF need to be one-hot",
            "amount": 200
          },
          {
            "description": "484 Write VHDL to expose CR and XER from Microwatt so single-stepping is possible",
            "amount": 150
          },
          {
            "description": "493 DMI JTAG TAP needed",
            "amount": 400
          },
          {
            "description": "wrapup",
            "amount": 100
          }
        ]
      },
      {
        "title": "384 Documentation for the Libre-SOC Power ISA Core and internal architecture",
        "intro": [
          "https://bugs.libre-soc.org/show_bug.cgi?id=384\n "
        ],
        "amount": 6900,
        "url": "{{ https://bugs.libre-soc.org/show_bug.cgi?id=384 }} ",
        "milestones": [
          {
            "description": "401 Convert Memory Architecture diagram from hand-drawn to editable SVG\n(Sub-sub-task of 389)",
            "amount": 150
          },
          {
            "description": "651 Convert bitmap images to vector svg - multi i/o dep cell and multi func unit\n(Sub-sub-task of 389)",
            "amount": 300
          },
          {
            "description": "404 adding nmigen-soc as a dependency needs documentation updated",
            "amount": 100
          },
          {
            "description": "460 Documenting the Out of Order architecture",
            "amount": 500
          },
          {
            "description": "472 tutorial and dev page needed for mesa driver",
            "amount": 100
          },
          {
            "description": "556 document SV OpenPOWER",
            "amount": 900
          },
          {
            "description": "594 create nmigen RFC for Dynamic Partitioned signals support",
            "amount": 1500
          },
          {
            "description": "595 Convert image(jpg,...) to svg",
            "amount": 200
          },
          {
            "description": "612 dev-env-setup script needed to build trellis and nextpnr-ecp5",
            "amount": 150
          },
          {
            "description": "626 dev-env-setup script for verilator, ghdl, iverilog and cocotb",
            "amount": 250
          },
          {
            "description": "634 sphinx - build, install and interface with projects",
            "amount": 150
          },
          {
            "description": "654 dev-env-setup script for symbiflow (arty A7-100T)",
            "amount": 750
          },
          {
            "description": "660 \"First developer steps\" documentation page",
            "amount": 250
          },
          {
            "description": "714 Coriolis2 Installation as Normal User Script",
            "amount": 350
          },
          {
            "description": "717 Document Power ISA test API",
            "amount": 500
          },
          {
            "description": "733 document SimdSignal.__Slice__ as part of Partitioned SIMD RFC",
            "amount": 350
          },
          {
            "description": "878 image conversion explaining multi-issue",
            "amount": 400
          }
        ]
      }
    ],
    "rfp_secret": ""
  }
}