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| F4PGASlackBridge | <amuttur> Hi there! I wanted to know if anyone has used a board with a differential clock in Symbiflow? | 17:36 |
|---|---|---|
| josuah | @amuttur can I have a hint about what a differential clock is? | 17:47 |
| josuah | that got me curious :) | 17:48 |
| josuah | @amuttur I cannot answer diretctly, but I can point you to this: https://joelw.id.au/FPGA/CheapFPGADevelopmentBoards | 18:07 |
| tpb | Title: Cheap FPGA Development Boards | Joel's Compendium of Total Knowledge (at joelw.id.au) | 18:07 |
| F4PGASlackBridge | <amuttur> Of course! So usually, clocks are defined as a single ended clock (i.e clk). A differential clock has a positive and a negative part to it, but can be converted to a single ended clock in Vivado by using the clock wizard | 18:10 |
| F4PGASlackBridge | <amuttur> There's a buffer that does the same and I think it is called IBUFDS. But F4PGA has issues reading this during the packing stage of VPR even though it exists in the library. | 18:11 |
| josuah | thank you! That helped me getting on the rigth track. | 18:36 |
| josuah | @amuttur I encounter things like this: https://stackoverflow.com/questions/40096272/how-do-i-use-set-lvds-mode-on-lattice-ice40-pins-using-icestorm-tools | 18:38 |
| tpb | Title: verilog - How do I use set LVDS mode on Lattice ICE40 pins using ICESTORM tools - Stack Overflow (at stackoverflow.com) | 18:38 |
| josuah | if anything hardware-related, it should be somewhere like /usr/local/share/yosys/ | 18:39 |
| josuah | there are blackbox verilog files here, that might be able to control the hardware in order to do that (hopefully?) | 18:39 |
| josuah | and there might be documentation on yosyshq about that https://yosyshq.readthedocs.io/en/latest/ | 18:40 |
| tpb | Title: YosysHQ Documentation Library (at yosyshq.readthedocs.io) | 18:40 |
| josuah | but I have also often seen hardware features undocumented, or maybe just me not finding it... | 18:40 |
| josuah | maybe it is rather documented on the nextpnr-$X with $x a project for supporting a set of boards | 18:41 |
| josuah | so different people documenting it in different ways? maybe that is why I did not find it at first | 18:41 |
| F4PGASlackBridge | <amuttur> I see. But the synthesis portion is fine, so the Yosys library is okay. The issue occurs when it comes to VPR during the packing stage when it reads the eblif file produced by Yosys. It says IBUFDS is not recognized in the VPR library | 19:06 |
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