Thursday, 2022-05-12

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lkcljosuah, ok, the way it works is that to compile something to a bitstream you need two things:09:48
lkcl1) some HDL09:48
lkcl2) a constraints file09:48
lkclthe constraints file is what tells the nextpnr-$x to map individual NETLIST entries (pins) onto actual IO pads09:49
lkcla differential clock is a clock line that, rather than having one single pin that goes on and off, there are a *pair* of clock lines that, simultaneously, switch to the opposite direction09:50
lkcli.e. they are "differential"09:50
lkclthe convention to distinguish differential pair pins is, one ends with "P" the other ends with "N"09:51
lkclP for Positive, N for Negative09:51
lkclback to internal blocks09:53
lkclyosys does *not* know about constraints (the IO pads), it only knows about NETLISTs and the things that those nets connect to.09:54
lkclyou do have to have some sort of representation of e.g. the IBUFDS, as a black-box module, with the inputs and outputs, so that when the *use* of that module is passed over to nextpnr-$x (or VTR), the PnR tool knows what to do with it09:55
lkclok so here's a declaration - a model - of IBUFDS09:57
tpbTitle: vhdl - How to route a LVDS clock from FPGA input to output? - Electrical Engineering Stack Exchange (at
lkclso, now you can (after probably translating that to verilog) use an IBUFDS / OBUFDS as if it was some sort of "black box".09:58
lkclyou *do not* have to write the *contents* of that black box named IBUFDS / OBUFDS: just use it (as an external module)09:59
lkclyosys is intelligent enough to recognise this and will not complain (or, it shouldn't). it will simply pass through the black box - and all its netlists - IBUFDS.I, IBUFDS.IB, IBUFDS.O - to nextpnr-$x / VTR10:00
lkclnextpnr-$x / VTR will go, "oh, you wanted an IBUFDS, and you're compiling for ICE40? sure, i recognise those, let me just wire that up and P&R it for you"10:01
lkclso it's actually extremely straightforward10:01
lkclthe only tricky bit, as you're finding out, is that none of this direct-interfacing with FPGA blocks is really properly documented, you're pretty much just expected to "work it out"10:03
lkclsometimes not even the FPGA designers properly provide documentation, one good example is the Lattice ECP5 JTAG block, which allows you to tap into the JTAG port and insert your own commands so that you can interact with openocd via the ECP5's JTAG port10:04
lkclsomeone had to actually reverse-engineer the ECP5's JTAG block10:04
lkclbut, your first priority is to find the "model" of the ICE40 IBUFDS.10:05
lkclthe one i found above i just saw it's for Xilinx FPGAs (sigh) despite (sigh) searching on gooogle "ICE40 IBUFDS". getting really irritating that google "helpfully" puts in additional unrelated searches to the keywords10:06
lkclsources where you should definitely find a model file (IBUFDS.v and/or IBUFDS.vhdl) will be in the Lattice (proprietary) SDK10:07
lkclbeyond that, you're into playing the "hunt the unknown reverse-engineered thing on the internet" game.10:08
tntNo such thing as IBUFDS in an ICE40. It's SB_IO10:20
josuahlkcl: great overview, thank you11:38
* josuah takes a cup of tea and reads11:38
josuahlkcl: that confirms what I was supposing, thank you for providing me that ground13:11
josuahthere might be a way to get around the name of what to search through the vendor's documentation13:11
josuahfor ICE40 and SB_IO (thanks tnt):
josuahthat makes a starting point to search in the meantime it gets better13:14
josuah@amuttur if you are still around: -> Using Differential I/O13:25
josuahthat could be what you need if your board is the iCE40...13:25
josuahlkcl: may I quote what you said? It could be useful to some.13:26
josuahlkcl: anonymously or not as you would prefer13:27
josuah <- I reworded slightly ('s -> is and alike for chat -> article conversion)13:43
tpbTitle: (at
lkclsure, no problem. do put a link to the irclogs - both i and mithro run irclog2html... 1 sec...15:24
tpbTitle: Thursday, 2022-05-12 (at
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josuahlkcl: thank you! changed on my side.15:49
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lambdaHi, did something in the build pipeline for the prebuilt f4pga-arch-defs files break? Unfortunately I can't look at at all without a google account, but, which I've been using so far, points to a build from March.17:01
tpbTitle: Anmelden – Google Konten (at
F4PGASlackBridge<amuttur> @josuah Thank you! My board is from Xilinx though. I can implement the differential clock on Vivado, but I wanted to see if someone did it on F4PGA cause I couldn't find a lot of documentation about it17:09
lkclamuttur: ah! then that link i found above *is* relevant :)17:12
lkclwhich FPGA is it?17:12
lkclyou should be able to extract the following from the vivado compilation:17:13
lkcl1) the verilog model for IBUFDS.v17:14
lkcl2) the constraints file (.xcf? something like that)17:14
lkcl3) if you used some sort of wizard, at least it will have created the verilog source *using* an IBUFDS instance which you can cut/paste out17:16
lkclbasically you have to do everything as text files / source-code files, so need to know a little bit more about how symbiflow / nextpnr-xilinx actually work17:16
lkclwhich board and which FPGA are you using?17:17
F4PGASlackBridge<amuttur> I'm using the AC 701 evaluation kit from Xilinx, it's Artix-7 series18:02
F4PGASlackBridge<amuttur> Yup, I used the clk_wiz.v verilog instantiation, but F4PGA has trouble understanding the IBUFDS cell18:02
F4PGASlackBridge<umartinezcorral> @mliberty could you get it to work?18:36
F4PGASlackBridge<mliberty> I think I know how to make it work but haven't had a chance yet to try it out.  I'll ping you if I need more help.  Thanks!18:37
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F4PGASlackBridge<amuttur> ```# Building complex block graph # Building complex block graph took 0.06 seconds (max_rss 71.0 MiB, delta_rss +0.0 MiB) # Load circuit # Load circuit took 0.00 seconds (max_rss 71.0 MiB, delta_rss +0.0 MiB) Error 1: Type: Blif file File: top.eblif Line: 639 Message: Failed to find matching architecture model for 'IBUFDS'```20:12
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