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| F4PGASlackBridge | <nishantpani95> Hi everyone | 10:58 |
|---|---|---|
| F4PGASlackBridge | <nishantpani95> I am a Master's student in ECE | 10:58 |
| F4PGASlackBridge | <nishantpani95> This semester I took a course in EDA algorithms and OS | 11:00 |
| F4PGASlackBridge | <nishantpani95> With all my experiences the f4pga project looked like a good project to refine my HDL, C++ and EDA skills | 11:01 |
| F4PGASlackBridge | <nishantpani95> Before my masters I worked with FPGAs in a few places | 11:01 |
| F4PGASlackBridge | <nishantpani95> So last in this year's GSOC one of the suggested ideas was integrating DSP48E for the Xilinx FPGAs is that still in the roadmap? | 11:02 |
| F4PGASlackBridge | <nishantpani95> Because I think I would like to work on it from January onwards outside GSOC | 11:02 |
| F4PGASlackBridge | <nishantpani95> Is there someone I can speak more with about this? | 11:03 |
| F4PGASlackBridge | <kgugala> Hi @nishantpani95, yes the DSP is still in the roadmap | 11:07 |
| F4PGASlackBridge | <kgugala> you can probably reach me and @tmichalak about this | 11:07 |
| F4PGASlackBridge | <nishantpani95> Hey @kgugala, thanks for the clarification. So my first question before I ask more, is what part of the codebase should I start looking at so that I can have a definite proposal. I also have a Basys3 board with me which might be useful for testing | 11:14 |
| F4PGASlackBridge | <nishantpani95> I have already downloaded the UG from AMDs website and started reading through the document | 11:14 |
| F4PGASlackBridge | <kgugala> there are two parts of this - prjxrays fuzzers and architecture definitions | 11:23 |
| F4PGASlackBridge | <kgugala> DSPs are hardblocks so we need to figure out how they are connected to the rest of the FPGA and what parameters controls them (and how are those encoded) | 11:24 |
| F4PGASlackBridge | <kgugala> there is already some fuzzer code here https://github.com/f4pga/prjxray/tree/master/fuzzers/101-dsp-pips and here https://github.com/f4pga/prjxray/tree/master/fuzzers/100-dsp-mskpat | 11:24 |
| F4PGASlackBridge | <kgugala> it'd be good to check if it covers all we need | 11:24 |
| F4PGASlackBridge | <nishantpani95> So if I understand correctly the purpose of the fuzzer code that you linked above is to figure out how DSP blocks fit in the FPGA model that exists? | 11:26 |
| F4PGASlackBridge | <kgugala> fuzzers are to understand how certain FPGA blocks are encoded in the bitstream | 11:27 |
| F4PGASlackBridge | <nishantpani95> and once that part is done the next step would be to understand the detailed working on the DSPs to get the architecture definitions ? | 11:28 |
| F4PGASlackBridge | <kgugala> there is also some code adding DSP primitive to VPR architecture definitions https://github.com/f4pga/f4pga-arch-defs/tree/main/xilinx/common/primitives/dsp48e1 | 11:28 |
| F4PGASlackBridge | <kgugala> it'd be good to start with some example and try to run it through the flow | 11:28 |
| F4PGASlackBridge | <kgugala> and see where it explodes | 11:28 |
| F4PGASlackBridge | <nishantpani95> Thanks I will dive into a bit | 11:29 |
| nimh | @nishantpani95 https://scholarworks.umass.edu/cgi/viewcontent.cgi?article=2318&context=masters_theses_2 | 11:39 |
| nimh | some other work done on that | 11:39 |
| nimh | I'm not sure that's how the slackbridge works? | 11:41 |
| F4PGASlackBridge | <nishantpani95> Thanks I have enough starter material for 2 weeks | 11:46 |
| F4PGASlackBridge | <nishantpani95> What is the slackbridge? | 11:47 |
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