Tuesday, 2022-12-13

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F4PGASlackBridge<nishantpani95> Also is it true that for development it is preferable to use Vivado 2017.1?15:24
F4PGASlackBridge<nishantpani95> I read it on some GitHub issue15:24
F4PGASlackBridge<kgugala> 2017.2 actually15:32
F4PGASlackBridge<kgugala> with newer ones you may hit some issues with crititcal warnings related to LUT6_215:33
F4PGASlackBridge<kgugala> we have a bridge connecting slack channel with IRC channel15:33
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F4PGASlackBridge<hansfbaier> @nishantpani95 You can talk with me too, I am currently working on Xilinx FPGAs and DSP48E is also on my TODO list21:37
F4PGASlackBridge<nishantpani95> Great I will definitely do that once I understand what has been done till now21:37
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F4PGASlackBridge<hansfbaier> @tmichalak, @kgugala Currently, DDR3 memory is not working yet on the high performance banks, and I have just isolated the cause: In SSTL15, the iob18 fuzzer does find the bit RIOB18.IOB_Y1.SSTL12_SSTL135_SSTL15.IN, and for all Y1 pads, reading/writing DDR3 memory works. *BUT*: the in IOB_Y0 (the upper pad in the IO tile) fuzzer does not find the bit RIOB18_X73Y25.IOB_Y0.SSTL12_SSTL135_SSTL15.IN , because of no23:00
F4PGASlackBridgecandidates, so I cannot set SSTL15 pads to input.  I created two super simple designs in verilog (one with SSTL15 pin on Y1 and one on Y0), and bit2fasm gives those unknown bits: On Y0: ```{ unknown_bit = "004424a7_23_27", unknown_segment = "0x00442480", unknown_segbit = "39_763" } { unknown_bit = "004424a7_54_31", unknown_segment = "0x00442480", unknown_segbit = "39_1759" } { unknown_bit = "004424a7_76_27", unknown_segment23:00
F4PGASlackBridge= "0x00442480", unknown_segbit = "39_2459" }```23:00
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