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F4PGASlackBridge | <hansfbaier> @tmichalak @kgugala I grepped through the specimens, but there seem to be enough specimens that have both LVCMOS and SSTL in its params.csv. So I don't see a reason, why segmatch should not be able to find the feature we are looking for. | 19:42 |
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F4PGASlackBridge | <hansfbaier> @tmichalak @kgugala Could it be acceptable that I just insert `RIOB18.IOB_Y0.SSTL12_SSTL135_SSTL15.IN` using sed? But the segmatch failure here seems to point to a deeper issue, but I don't currently feel capable of getting to the bottom of this, because I do not understand of how segmatch works. | 19:44 |
F4PGASlackBridge | <hansfbaier> This here looks suspicious though: | 19:48 |
F4PGASlackBridge | <tmichalak> If the tag was 0 and the bit was there in the segment then this would be an explanation why segmatch doesn't find the bit. But segdata is formed as seg bit tag so the top red arrow refers actually to the previous segment, the tags for the bits pointed by the lower arrow are lower down | 19:51 |
F4PGASlackBridge | <hansfbaier> Ah | 19:51 |
F4PGASlackBridge | <hansfbaier> @tmichalak There seem to be contradictions. I write this python script to find them, and attached the result also | 20:46 |
F4PGASlackBridge | <hansfbaier> At first glance it looks like the contradictions only seem to occure if IN_DIFF = 1 | 20:48 |
F4PGASlackBridge | <hansfbaier> So for that I'd probably have to set .IN 0 | 20:48 |
F4PGASlackBridge | <hansfbaier> Yes exactly! I updated the script to check if the contradictions only occur for IN_DIFF = 1, and it is the case! | 21:00 |
F4PGASlackBridge | <hansfbaier> Then I think I have a fix | 21:00 |
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F4PGASlackBridge | <hansfbaier> @tmichalak This is how the results look after the fix | 21:52 |
F4PGASlackBridge | <hansfbaier> LVDS.IN_DIFF has disappeared | 21:55 |
F4PGASlackBridge | <hansfbaier> grr | 21:55 |
F4PGASlackBridge | <hansfbaier> Yes but DDR3 still works in the design. | 21:57 |
F4PGASlackBridge | <hansfbaier> I've got to make my fix conditional to SSTL | 21:59 |
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F4PGASlackBridge | <hansfbaier> @tmichalak Actually LVDS is fine, it just doesn't seem to combine it anymore: ``` Orig line: RIOB18.IOB_Y0.LVDS_SSTL12_SSTL135_SSTL15.IN_DIFF origin:030-iob18 !39_127 38_126 39_01 New line : RIOB18.IOB_Y0.LVDS.IN_DIFF !39_127 38_126 39_01``` | 22:18 |
F4PGASlackBridge | <hansfbaier> Grrr | 22:19 |
F4PGASlackBridge | <hansfbaier> I wonder why | 22:23 |
F4PGASlackBridge | <hansfbaier> Ah moment | 22:28 |
F4PGASlackBridge | <hansfbaier> @tmichalak This are the resulting changes in the database now. Do you think it makes sense? | 22:38 |
F4PGASlackBridge | <hansfbaier> .IN looks fine, but .IN_DIFF is slightly confusing now | 22:44 |
F4PGASlackBridge | <hansfbaier> Still works on the hardware for DIFF_SSTL15 though, but I am not sure about LVDS | 22:45 |
F4PGASlackBridge | <hansfbaier> DDR3 works with these changes. Got to test LVDS. | 22:56 |
F4PGASlackBridge | <hansfbaier> @tmichalak The changes break a blinky on the STLV7325 board. (differential clock input not working neither as SSTL15 nor as LVDS). | 23:09 |
F4PGASlackBridge | <hansfbaier> So I am back to square one: How about just fixing up the db by adding the manually discovered feature with sed? | 23:09 |
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