| openpowerbot | [slack] <Benjamin Herrenschmidt> @Paul Mackerras Did anybody ever get to the bottom of why UART output is corrupted for a few thousands cycles during boot ? | 00:29 |
|---|---|---|
| openpowerbot | [slack] <Paul Mackerras> nope | 00:29 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> I have the thing getting up now on the Wukong board (A100T speed grade 1), no timing violations, and I get crap | 00:29 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> Fun... if I add liteeth to the build, it doesn't boot (it doesn't get to sdram init) | 00:41 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> some debugging will be needed ... another day 🙂 | 00:41 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> @joel @Paul Mackerras did we land on something for dealing with DTBs and the various microwatt options ? | 04:02 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> at the moment we have a dtb which hard wires 256MB of RAM and liteeth | 04:02 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> unless we want to do real dtb creation in sdram_init in mw itself... | 04:03 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> (but that will be at the expense of block ram/rom) | 04:03 |
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| openpowerbot | [slack] <Benjamin Herrenschmidt> @Paul Mackerras @Anton Blanchard Did we ever get a SPI flash driver ? I know I had written one for Linux at some point and I think lost it 🙂 | 04:10 |
| openpowerbot | [slack] <joel> Fixing up the device tree with arch/powerpc/boot/microwatt.c is kinda neat | 04:19 |
| openpowerbot | [slack] <Paul Mackerras> Or we could get u-boot to fix the device tree 🙂 | 04:23 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> who is using uboot ? 🙂 | 04:28 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> I don't see the point here 🙂 | 04:28 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> do we have upstream drivers for spi and litesdcard ? | 04:28 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> also if somebody is using the olimex tiny-h, I have a patch for urjtag to fix the detection | 04:29 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> @Paul Mackerras I was thinking of setting no_bram=true memory_size=0 as default for all the "dram" targets, any reason not to ? | 04:47 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> @Anton Blanchard ^ | 04:47 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> otherwise we waste BRAM space in the init BRAM for a payload that generally doesn't exist | 04:48 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> and we won't boot from flash | 04:48 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> (or is too small since firmware.hex really wants more than we can fit in the init rams) | 04:49 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> HRM... we can't really change the defaults per target | 04:52 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> fusesoc is a bit limitative | 04:52 |
| openpowerbot | [slack] <mithro> @Benjamin Herrenschmidt You know there is a great SoC generator which includes Microwatt (and 12 other CPU cores) and a directly supports all these awesome LiteX cores like LiteDRAM, LiteEth, LiteSATA, LiteSPI, with all their configuration options | 04:55 |
| openpowerbot | [slack] <mithro> @Benjamin Herrenschmidt It's called.... LiteX! | 04:55 |
| openpowerbot | [slack] <joel> and it doesn't boot 😉 | 04:55 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> @mithro 🙂 | 04:56 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> I'm also doing patches to "fix" Wukong v2 support in LiteX .. and we should look into why | 04:56 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> @mithro I think microwatt is slower in LiteX though... | 04:56 |
| openpowerbot | [slack] <mithro> @Benjamin Herrenschmidt Then we should fix that | 04:56 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> no pipelined wishbone among others, doesn't have my fancy L2 cache 🙂 | 04:56 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> yeah well... either we make a pipelined wishbone in LiteX or we add native AXI support to mw | 04:57 |
| openpowerbot | [slack] <mithro> @Benjamin Herrenschmidt I'm working on trying to get some better CI (including on-device testing) going for LiteX and related projects | 04:57 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> yeah my latest PR to litedram has the CI failing for obscure reasons. the log has nothing useful | 04:57 |
| openpowerbot | [slack] <mithro> @Benjamin Herrenschmidt I'm all for a pipelined wishbone in LiteX -- Charles Papon the author of VexRISCV has also expressed interest in that | 04:58 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> yup, pipelined wb is a lot simpler than AXI and gives significant benefits for cache line loads and pipelined stores | 04:58 |
| openpowerbot | [slack] <mithro> @Benjamin Herrenschmidt The test doesn't fail locally for you? | 04:58 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> ok, Linux up on the Wukong, pfiew | 04:58 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> @mithro I don't know, I haven't tried to figure out how to run the tests locally yet 🙂 | 04:59 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> been ... busy | 04:59 |
| openpowerbot | [slack] <mithro> https://antmicro.com/blog/2021/08/open-source-github-actions-runners-with-gcp-and-terraform/ | 04:59 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> I cannot dedicate the time I used to last year on this stuff 🙂 | 04:59 |
| openpowerbot | [slack] <mithro> @Benjamin Herrenschmidt Do I recall you are at Amazon? | 04:59 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> yup | 04:59 |
| openpowerbot | [slack] <mithro> We should figure out how to get them onto the open source EDA train! :-) | 05:01 |
| openpowerbot | [slack] <mithro> OpenROAD continues to get better very quickly | 05:01 |
| openpowerbot | [slack] <mithro> @Benjamin Herrenschmidt Do you know if internally Amazon team doing the ARM ASIC stuff is a SystemVerilog or VHDL or other shop internally? | 05:02 |
| openpowerbot | [slack] <mithro> BTW I **am** very supportive of FuseSoC in general -- I'm funding Kate Temkin to do "auto integration" between nmigen and FuseSoC (IE nmigen can import any FuseSoC core and any nmigen can be used as a FuseSoC) | 05:05 |
| openpowerbot | [slack] <mithro> I just really want to see microwatt work better when used **inside** LiteX like both mor1kx, rocket and vexriscv do | 05:06 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> I don't know but probably verilog | 05:08 |
| openpowerbot | [slack] <Paul Mackerras> fair enough - if only object-oriented python didn't look quite so much like magic spells 🙂 | 05:08 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> 🙂 | 05:08 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> the main thing for microwatt to not suck in litex is pipelined wb and possibly a port of my smart-ass l2 | 05:08 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> the second thing is we need to sort out the dtb gen and sysconf in a way that 's compatible between litex and native microwatt or at least a way for sysconf to tell that it's litex | 05:09 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> @joel you never adding MDIO support to the PHY ? that .. sucks 🙂 | 05:10 |
| openpowerbot | [slack] <joel> Patches welcome | 05:10 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> interestingly enough the liteeth HW seems to try to auto-detect MII vs GMII ... most NICs rely on software to set the right bit after polling the PHY | 05:10 |
| openpowerbot | [slack] <joel> Probably make sense to add some mdio hardware to liteeth first. It's just a bitbang interface; all it exposes is the gpio | 05:10 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> haha yeah, shouldn't be hard... I thought we did a while back | 05:10 |
| openpowerbot | [slack] <joel> nah, we skipped out on it because it didn't need it | 05:11 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> bitbang is fine for MDIO | 05:11 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> ok | 05:11 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> well it doesn't expose link up /down as a result | 05:11 |
| openpowerbot | [slack] <joel> Yeah. I started writing the code to use linux's existing bitbang driver, but the probing did my head in | 05:11 |
| openpowerbot | [slack] <joel> the device tree stuff for that is a maze | 05:11 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> ```# ifconfig eth0 up 10.2.1.12 netmask 255.255.255.0 | 05:11 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> # [ 816.167773] liteeth c8021000.ethernet eth0: LITEETH_READER_READY not ready``` | 05:11 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> you don't need DT if you have MDIO, you can jsut probe | 05:12 |
| openpowerbot | [slack] <joel> Ok | 05:12 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> hrm ... liteeth is not happy | 05:12 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> could that this gmii detection isn't quite right | 05:13 |
| openpowerbot | [slack] <joel> Looks like you found a bug. There's also a bug in the core that has made funny stuff happen recently. I think Paul and Anton are on it | 05:13 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> right now it just doesn't work on this board | 05:15 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> it's using the GMII_MII ... but I tried forcing the peer to either mode to no avail | 05:16 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> I should try on arty | 05:17 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> @joel your start_xmit is racy vs your interrupt too | 05:20 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> I think it would help if we brought some of the PHY layer (not the PHY chip, but liteeth GMII/MII layer) state signals up to registers for debug | 05:21 |
| openpowerbot | [slack] <mithro> I'm pretty sure I had bit banging MDIO working on the mor1kx a long while ago... | 05:21 |
| openpowerbot | [slack] <Paul Mackerras> @mithro is there a way for litex to set generic parameters for the vhdl it's importing? | 05:21 |
| openpowerbot | [slack] <mithro> @Paul Mackerras I don't do much VHDL so don't know off the top of my head -- but I'm pretty sure there is | 05:22 |
| openpowerbot | [slack] <Paul Mackerras> presumably the vhdl gets converted to verilog by ghdl or something? | 05:23 |
| openpowerbot | [slack] <mithro> If I had an example of VHDL generic parameters working in pure VHDL I could probably quickly figure out how to get LiteX to generate the same stuff | 05:23 |
| openpowerbot | [slack] <Paul Mackerras> as a for-instance we can set generic parameters via fusesoc from the fusesoc command line | 05:25 |
| openpowerbot | [slack] <Paul Mackerras> so for example putting --has_fpu on the command line sets the HAS_FPU generic (which is a boolean) to true | 05:25 |
| openpowerbot | [slack] <mithro> @Paul Mackerras Do you mean controlling these things -> https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/microwatt/microwatt_wrapper.vhdl#L17-L20 ? | 05:29 |
| openpowerbot | [slack] <mithro> @Paul Mackerras Do you mean controlling these things -> https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/microwatt/microwatt_wrapper.vhdl#L17-L20 ? | 05:29 |
| openpowerbot | [slack] <Paul Mackerras> yes those kind of things (though there are now quite a few more than that) | 05:29 |
| openpowerbot | [slack] <mithro> And https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/microwatt/microwatt_wrapper.vhdl#L95-L98 | 05:29 |
| openpowerbot | [slack] <mithro> And https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/microwatt/microwatt_wrapper.vhdl#L95-L98 | 05:29 |
| openpowerbot | [slack] <mithro> I have no idea why migen does this -- but if you pass `p_XXX=True` to the the migen Instance class which is wrapping the module (in the same way that `i_XXX` becomes an input port and `o_XXX` becomes an output port), it should end up setting those "parameters" in Verilog / SystemVerilog speak | 05:31 |
| openpowerbot | [slack] <mithro> See the mor1kx example -> https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/mor1kx/core.py#L95-L127 | 05:32 |
| openpowerbot | [slack] <mithro> See the mor1kx example -> https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/mor1kx/core.py#L95-L127 | 05:32 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> @joel as pasted privately, LiteX randomly changing CSRs strikes back with your driver | 05:36 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> the layout already doesn't match what LiteX generated | 05:36 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> I had that conversation with the LiteX folks more than a year ago, it was somewhat agreed to have some kind of "templates" taht could fix the format for some registers but it looks like no action was taken | 05:36 |
| openpowerbot | [slack] <joel> Those #defines are from 2017, it's been mostly stable since then. But you're right, we need to fix the layout, because that's just by accident they haven't changed | 05:36 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> in the case I pasted, depending on what MII layer you build you get a different layout | 05:37 |
| openpowerbot | [slack] <joel> Okay. Good thing I didn't upstream the mii code 😄 | 05:37 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> so it's not even "changes in the source" ... it's purely how you configure liteeth | 05:37 |
| openpowerbot | [slack] <mithro> @Benjamin Herrenschmidt Doesn't the device tree let you set the offset for the various registers? | 05:37 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> no | 05:38 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> and that would be an insane amount of bloat | 05:38 |
| openpowerbot | [slack] <mithro> Did that functionality get reverted? | 05:38 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> besides the way CSR works even the bit layout can change | 05:38 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> well there might be some bloated stuff somewhere people use... but it's gross at best | 05:39 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> and liteeteh driver that went upstream definitely doesn't use it | 05:39 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> I mean you do those little cores and you make them run 3247983274 instructions for register access | 05:39 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> because you can't be bothered creating a half sane standard layout for your IP... | 05:39 |
| openpowerbot | [slack] <mithro> The states of various Linux drivers (and Zephyr) drivers and their various emulation models for the hardware can be found https://docs.google.com/spreadsheets/d/1XTHfdYXuvwoYdPXm4M6qDA0D2fZCPy220-9q6qZpTw4/edit#gid=1131619550 | 05:39 |
| openpowerbot | [slack] <Paul Mackerras> @Benjamin Herrenschmidt don't you realise that every time you change a line of HDL code you should be creating a completely new entire bespoke software stack for it? 🙂 | 05:40 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> Yeah that's pretty much the mindset | 05:41 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> reminds me of Dan Malek :_) | 05:41 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> (I always in my mind called him the Dalek 🙂 | 05:41 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> @mithro All those Linux drivers hard wire the CSR offsets | 05:44 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> they will break randomly because LiteX doesn't have a mechanism to even try keeping them somewhat stable | 05:44 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> Ahhh | 05:46 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> @joel it fails here because the registers are the wrong layout | 05:46 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> ```ethernet@8020000 { | 05:47 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> compatible = "litex,liteeth"; | 05:47 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> reg = <0x8021000 0x100 | 05:47 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> 0x8020800 0x100 | 05:47 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> 0x8030000 0x2000>; | 05:47 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> reg-names = "mac", "mido", "buffer"; | 05:47 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> litex,rx-slots = <2>; | 05:47 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> litex,tx-slots = <2>; | 05:47 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> litex,slot-size = <0x800>; | 05:47 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> interrupts = <0x11 0x1>; | 05:47 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> };``` | 05:47 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> ```csr_base,ethphy,0x00000000,, | 05:47 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> csr_base,ethmac,0x00000800,, | 05:47 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> csr_base,ctrl,0x00001000,,``` | 05:47 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> you have MAC at 0 and PHY at 0x800 but what LiteX generated is the other way around | 05:47 |
| openpowerbot | [slack] <joel> It's correct for the liteeth that we have checked in | 05:47 |
| openpowerbot | [slack] <joel> I think Anton reverts the AutoCSR patch from LiteX when re-building, in order to have it match | 05:48 |
| openpowerbot | [slack] <joel> We really should have upstreamed the layout that autocsr generates... | 05:48 |
| openpowerbot | [slack] <joel> what a mess, already | 05:48 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> I told the LiteX folks that was going to be a mess almost 2 years ago I think | 05:48 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> before COVID for sure | 05:48 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> but it doesn't appear anything was done | 05:48 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> do you know what Anton did exactly ? | 05:49 |
| openpowerbot | [slack] <joel> Author: Anton Blanchard <mailto:anton@linux.ibm.com> | 05:50 |
| openpowerbot | [slack] <joel> Date: Mon Aug 9 13:25:58 2021 | 05:50 |
| openpowerbot | [slack] <joel> | 05:50 |
| openpowerbot | [slack] <joel> liteeth: Regenerate from upstream litex | 05:50 |
| openpowerbot | [slack] <joel> | 05:50 |
| openpowerbot | [slack] <joel> Unfortunately the CSR layout has shifted on upstream litex, so this | 05:50 |
| openpowerbot | [slack] <joel> is built with the following litex patch backed out: | 05:50 |
| openpowerbot | [slack] <joel> | 05:50 |
| openpowerbot | [slack] <joel> aad56a047a33 ("integration/soc: Use CSR automatic allocation.") | 05:50 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> where did you get this ? | 05:50 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> anton has a fork of liteeth ? | 05:50 |
| openpowerbot | [slack] <joel> that commit message is from microwatt | 05:50 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> ah no sorry, ignore me | 05:51 |
| openpowerbot | [slack] <joel> https://github.com/shenki/litex/tree/autocsr-revert | 05:51 |
| openpowerbot | [slack] <joel> https://github.com/shenki/litex/commit/cf1a5c3a0633d58271c411f6d17c731c3be3969d.patch | 05:51 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> yup I got it but that's not sustainable as new stuff gets added that doesn't have the old school adding code | 05:52 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> I can't believe nobody has even tried to address this in LiteX ... in fact have made it worse | 05:53 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> ok liteeth working now | 05:56 |
| openpowerbot | [slack] <mithro> @Paul Mackerras Did my suggestion for the generics work / help? | 06:12 |
| openpowerbot | [slack] <Paul Mackerras> @mithro I'm deep in something else right at the moment but I'll stash that away for when I get to look at it | 06:13 |
| openpowerbot | [slack] <mithro> @Paul Mackerras No worries, if it doesn't work (which wouldn't surprise me) do poke me and I can probably help you debug pretty quickly | 06:19 |
| openpowerbot | [slack] <Paul Mackerras> thanks | 06:19 |
| openpowerbot | [slack] <mithro> @Paul Mackerras My evenings are generally pretty free due to most of my collaborators being in europe | 06:20 |
| openpowerbot | [slack] <mithro> @Benjamin Herrenschmidt Well, if you find anyone inside Amazon doing SystemVerilog work -- we have the equivalent to clang-format and lint now -> https://antmicro.com/blog/2021/08/verible-integration-with-github-actions/ and https://antmicro.com/blog/2020/04/systemverilog-linter-and-formatter-in-fusesoc/ | 06:24 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> @Paul Mackerras some of the black magic in that python HDL is just painful and makes my brain explode | 06:35 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> I have constructs here I could **swear** are plain integers evaluated at litex gen time, but end up generating verilog conditionals | 06:35 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> that stuff is too smart by half, it's essentially incomprehensible outside of the 3 ppls who use it daily | 06:36 |
| lkcl | mithro: that's fantastic to hear about FuseSOC-nmigen. it's one of those combinations, "oink. why do these two not play nice together??" | 13:21 |
| lkcl | ktemkin's a brilliant engineer, that's a great choice | 13:21 |
| lkcl | also from what i can gather it is hosting-provider-independent. | 13:25 |
| lkcl | veeery little in the way of code comments (i.e. none) which is a little alarming | 13:25 |
| lkcl | https://github.com/olofk/fusesoc/blob/master/fusesoc/config.py | 13:25 |
| lkcl | this was my painful learning experience of "Not To Do Templating For Perphipheral-Interconnect": | 13:30 |
| lkcl | https://git.libre-soc.org/?p=pinmux.git;a=blob;f=src/bsv/pinmux_generator.py;hb=HEAD | 13:30 |
| lkcl | it worked, but it's something mad like a *seven* step process to integrate a new peripheral, and actually integrates the actual source code *of* the peripheral *into* the python code | 13:31 |
| lkcl | the pinmux part - the GPIO muxer - was done using code-fragments and PHP-style "templating" (exactly like how everyone else has ever done this) | 13:32 |
| lkcl | and i quickly learned it was absolute Hell. | 13:32 |
| lkcl | the next implementation i will use nmigen and *dynamic* allocation of objects. | 13:34 |
| lkcl | nmigen-soc but *NOT* auto-generating nmigen-soc *CODE*, actually *dynamically* at runtime instantiating nmigen-soc objects with the prerequisite CSRs etc. etc. | 13:35 |
| lkcl | very similar to litex but without the fragile-ness that is inherent with migen | 13:35 |
| lkcl | Ben: i spoke with Paul yesterday, about the DMI interface in Microwatt. | 13:36 |
| lkcl | i learned that core_debug.vhdl you wrote *only* handles the core (regs, start/stop) | 13:37 |
| lkcl | and that there *is* actually DMI-memory-access... | 13:37 |
| lkcl | here https://github.com/antonblanchard/microwatt/blob/master/wishbone_debug_master.vhdl | 13:37 |
| lkcl | but (whoopsie) it's not documented (which is why i missed it and added a JTAG-to-Wishbone mechanism in Libre-SOC) | 13:38 |
| lkcl | ha! | 13:38 |
| lkcl | https://github.com/antonblanchard/microwatt/blob/0a415410c9f75e4fd8699c70b43dc26d4114d6ed/wishbone_debug_master.vhdl#L89 | 13:38 |
| lkcl | so that *is* actually doing auto-increment of the address register :) | 13:39 |
| lkcl | exactly as you said so as to do "optimised streaming" over DMI :) | 13:39 |
| lkcl | so basically that code takes the top few bits of the DMI address, and goes "if set to this then it's to be interpreted as doing DMI-memory-access" | 13:40 |
| lkcl | if set to "the other then we send it on to core_debug.vhdl" | 13:40 |
| lkcl | so, wishbone_debug_master.vhdl *is* actually implementing the exact same protocol / system i described here | 13:41 |
| lkcl | https://libre-soc.org/irclog-microwatt/%23microwatt.2021-09-18.log.html#t2021-09-18T15:45:32 | 13:41 |
| lkcl | funny / doh moment | 13:41 |
| lkcl | mithro: FuseSOC has two NLnet Grants that i can identify https://nlnet.nl/project/FuseSoc-Cores/ https://nlnet.nl/project/Edalize-ASIC/ | 13:43 |
| lkcl | i'd be happy to assist in putting together a Grant Proposal to NLnet ktemkin to work on FuseSOC-nmigen | 13:43 |
| lkcl | that would take some of the "financing burden" off of your budget. | 13:44 |
| lkcl | Gustavo: i spoke to Paul yesterday about the DMI "waiting" issue, did you get a chance to raise a bugreport? | 15:29 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> Is http://radiona.org/ulx3s/ any good for microwatt hacking ? Xilinx is annoying me and I'd like to play with open tools a bit more 🙂 | 23:49 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> but I have no experience with ECP5 | 23:49 |
| lkcl | yes it works great | 23:58 |
| lkcl | we have a script already done which makes it possible to run microwatt on the ulx3s | 23:58 |
| lkcl | however bear in mind it only has 32 MB SDRAM1 | 23:58 |
| lkcl | if you get a VERSA_ECP5 it's in stock from digikey | 23:59 |
| lkcl | 1 sec | 23:59 |
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