| openpowerbot | [slack] <mithro> @Paul Mackerras Teo is also going to do a physical design layout like DFFRAM does | 00:11 |
|---|---|---|
| openpowerbot | [slack] <Anton Blanchard> Nice! On our sky130 submission the 64 bit multiplier was enormous. We had so much area we didn't bother to optimise it in any way. Would be great to have better options here | 00:13 |
| openpowerbot | [slack] <Anton Blanchard> Even worse - we rely on register retiming in the tools, and that doesn't work on OpenROAD. So we had a bunch of useless stages 🙂 | 00:13 |
| openpowerbot | [slack] <Anton Blanchard> Speaking of sky130... Interested in doing something for the third shuttle? @Paul Mackerras @Michael Neuling @Benjamin Herrenschmidt @joel (and anyone else!) | 00:45 |
| openpowerbot | [slack] <Anton Blanchard> Many of the things that we really struggled with on the first shuttle are now fixed, so it should be a lot less pain | 00:46 |
| openpowerbot | [slack] <Paul Mackerras> sounds interesting, how many gates do we get? | 00:47 |
| openpowerbot | [slack] <Anton Blanchard> On the first shuttle, issues with the tools tended to be the limit, eg https://github.com/The-OpenROAD-Project/OpenROAD/pull/602 | 00:49 |
| openpowerbot | [slack] <Anton Blanchard> tracks in space! | 00:49 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> I have no background on any of this 🙂 | 00:55 |
| openpowerbot | [slack] <Anton Blanchard> @Paul Mackerras I need to look at my notes, but we were in the hundreds of thousands of gates. 1M seems reasonable, depends on what gates you use, the drive strength required and the routability of it all | 00:55 |
| openpowerbot | [slack] <Anton Blanchard> Good news, neither did I! | 00:55 |
| openpowerbot | [slack] <Anton Blanchard> I can drive the tools. The interesting questions are what we should put on (other than Microwatt) | 00:56 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> what IOs do we have ? | 00:56 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> UART and RMII would be good | 00:56 |
| openpowerbot | [slack] <Paul Mackerras> I was reading that the Cray-1 only used one type of IC for logic, and only 3 types overall, so apparently you can construct anything you like using 4-input and 5-input OR/NOR gates 🙂 | 00:56 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> SPI too, maybe SD if we have enough pins | 00:56 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> can we put litex things ? what about DDR RAM ? | 00:56 |
| openpowerbot | [slack] <Anton Blanchard> ~38 GPIOs. 100MHz ish | 00:57 |
| openpowerbot | [slack] <Anton Blanchard> Someone is playing with higher speed I/Os, not sure where they ended up | 00:57 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> RAM is going to be the thing that makes it useful or not ... | 00:57 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> ok 38 should be enough for all of the above (UART, RMII, SPI and maybe SD) | 00:57 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> plus a few spares | 00:57 |
| openpowerbot | [slack] <Anton Blanchard> Yep | 00:57 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> maybe we could build a GPIO mux so pins can be reconfigured | 00:58 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> (let's not get into clock gating the actual IP cores though 🙂 | 00:58 |
| openpowerbot | [slack] <Anton Blanchard> Hah yeah | 00:58 |
| openpowerbot | [slack] <Anton Blanchard> Right now we sit within a harness (RISC-V based). We've toyed with the idea of replacing it completely but that would be a chunk more work | 00:59 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> it might be interesting to ask a real HW person about the possibility of clock gating them without needing expensive synchronizers on the wb but that's for another day | 00:59 |
| openpowerbot | [slack] <Anton Blanchard> https://github.com/efabless/caravel | 00:59 |
| openpowerbot | [slack] <Anton Blanchard> @Paul Mackerras I followed up on the `ghdl` vs `verilator` performance question. Running our long micropython test, `ghdl` takes 7:06 and `verilator` 0:46, so `verilator` is definitely faster. | 01:02 |
| openpowerbot | [slack] <Anton Blanchard> But wait - did @Michael Neuling deconfigure the icache for all verilog targets? | 01:03 |
| openpowerbot | [slack] <Anton Blanchard> I hacked up jtag for shuttle 1. Be nice to integrate it better and get it merged https://github.com/antonblanchard/microwatt/commit/5e8ba5acb0e08656a2d04745b7c7939901d00676 | 01:06 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> we could test it using IO pins of the FPGA | 01:07 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> along with a random FTDI adapter | 01:07 |
| openpowerbot | [slack] <Anton Blanchard> Yeah | 01:07 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> I have several such adapters with varying speeds 🙂 | 01:07 |
| openpowerbot | [slack] <Anton Blanchard> Someone was experimenting with scan chains, would be nice to do that and hook it up to JTAG | 01:09 |
| openpowerbot | [slack] <Anton Blanchard> Might make the hardware somewhat debuggable 🙂 | 01:09 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> can you do that in FPGAs ? | 01:09 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> without wasting a ton of wires & gates | 01:09 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> actually for FPGA you can use the FPGA own logic to scan shit out | 01:09 |
| openpowerbot | [slack] <Anton Blanchard> No idea, this was in terms of the OpenROAD flow | 01:09 |
| openpowerbot | [slack] <Anton Blanchard> Yeah good point | 01:09 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> if you know how to do it ... it's complicated | 01:09 |
| openpowerbot | [slack] <Anton Blanchard> Configuring the icache to match `ghdl`, `verilator` slows just a little (53.7s). Still miles ahead | 01:12 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> Yes verilator is much faster, I remember going a fair way through booting linux in it 🙂 | 01:18 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> back in the days | 01:18 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> it used to be that the verilog was undebuggable but I think Tristan improved the name of the translated signals, didn't he ? | 01:18 |
| openpowerbot | [slack] <Anton Blanchard> Yeah a few things have got better wrt `ghdl` synthesis: | 01:24 |
| openpowerbot | [slack] <Anton Blanchard> • Records in ports are now exposed. All the wishbones are no longer a bag of undebuggable bits 🙂 | 01:24 |
| openpowerbot | [slack] <Anton Blanchard> • RAMs are now exposed with their name, so we can peek at the GPRs, SPRS etc. | 01:24 |
| openpowerbot | [slack] <Anton Blanchard> We could ask Tristan if he could expose the fields of records inside modules, that's probably the last big issue | 01:25 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> ok | 01:29 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> @Anton Blanchard we should look at having a make verilated-check that uses the verilated output for a quick pass | 01:30 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> easy to go back to vhdl once you idnetify the specific failing test | 01:31 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> (and we should probably refresh the test list with a bunch new stuff & new instructions etc...) | 01:31 |
| openpowerbot | [slack] <Anton Blanchard> We have a single test in the CI at least, runs micropython with the verilator build | 01:31 |
| openpowerbot | [slack] <Anton Blanchard> Would be nice to add some more complicated tests | 01:31 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> well, the existing make check at least | 01:32 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> and refresh that test list with newly generated ones that use more instructions etc... | 01:32 |
| openpowerbot | [slack] <Anton Blanchard> Yeah both would be nice | 01:32 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> anyway, I have real work to do now 🙂 ttyl | 01:33 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> btw, you usually build yosys with clang or gcc ? | 01:37 |
| openpowerbot | [slack] <Anton Blanchard> I haven't looked until just then, it seems like it uses clang by default? | 01:39 |
| openpowerbot | [slack] <Anton Blanchard> ```clang -o frontends/verilog/verilog_parser.tab.o``` | 01:39 |
| openpowerbot | [slack] <Anton Blanchard> Not sure why | 01:39 |
| openpowerbot | [slack] <joel> Is this how you run the verilator test? | 02:02 |
| openpowerbot | [slack] <joel> ``` | 02:02 |
| openpowerbot | [slack] <joel> Is this how you run the verilator test? | 02:02 |
| openpowerbot | [slack] <joel> ```$ make FPGA_TARGET=verilator DOCKER=1 test_micropython_verilator``` | 02:02 |
| openpowerbot | [slack] <joel> It errors out for me: | 02:02 |
| openpowerbot | [slack] <joel> ``` | 02:02 |
| openpowerbot | [slack] <joel> It errors out for me: | 02:02 |
| openpowerbot | [slack] <joel> ```docker run --rm -v /home/joel/dev/microwatt:/src:z -w /src verilator/verilator:latest -O3 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT -CFLAGS " -DCLK_FREQUENCY=50000000" -Iuart16550 --assert --cc --exe --build microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o microwatt-verilator -top-module toplevel | 02:02 |
| openpowerbot | [slack] <joel> %Warning-PINMISSING: microwatt.v:69794:12: Cell has missing pin: 'wb_sel_i' | 02:02 |
| openpowerbot | [slack] <joel> 69794 | uart_top \uart0_16550.uart0 ( | 02:02 |
| openpowerbot | [slack] <joel> | ^~~~~~~~~~~~~~~~~~ | 02:02 |
| openpowerbot | [slack] <joel> ... For warning description see https://verilator.org/warn/PINMISSING?v=4.211 | 02:02 |
| openpowerbot | [slack] <joel> ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message. | 02:02 |
| openpowerbot | [slack] <joel> %Error: microwatt.v:280:3: Cannot find file containing module: 'EHXPLLL' | 02:02 |
| openpowerbot | [slack] <joel> 280 | EHXPLLL #( | 02:02 |
| openpowerbot | [slack] <joel> | ^~~~~~~ | 02:03 |
| openpowerbot | [slack] <joel> ... Looked in: | 02:03 |
| openpowerbot | [slack] <joel> uart16550/EHXPLLL | 02:03 |
| openpowerbot | [slack] <joel> I build the tools from scratch and now it builds | 02:44 |
| openpowerbot | [slack] <Anton Blanchard> You probably had a leftover miccrowatt.v. The Makefile is pretty awful for handling changes in the verilog targets. I'm hoping fusesoc one day allows us to build our verilog, yosys etc targets | 02:48 |
| openpowerbot | [slack] <joel> I don't know what's going on. I just cleaned everything out and tried again, and now I'm back to failing with that same error | 02:54 |
| openpowerbot | [slack] <joel> Ah. That error is a symptom of forgetting to set FPGA_TARGET=verilator | 02:59 |
| openpowerbot | [slack] <Anton Blanchard> Yeah | 03:03 |
| openpowerbot | [slack] <Anton Blanchard> It's all pretty messy | 03:03 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> we should cleanup a lot of stuff like that | 04:52 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> such as moving vhdl files to sub directories etc.. 🙂 | 04:52 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> openocd to scripts/ | 04:52 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> and more | 04:52 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> the tree is a mess and the Makefiles are sordid 🙂 that said neither verilator nor ghdl make it easy | 04:52 |
| openpowerbot | [slack] <Paul Mackerras> time to fork the project! 🙂 | 04:56 |
| openpowerbot | [slack] <Michael Neuling> @Matt Johnston your orangecrab microwatt stuff looks great. Have you looked doing serial over valentyusb ? | 08:28 |
| openpowerbot | [slack] <Matt Johnston> haven't looked much yet, but I'd like to | 08:28 |
| openpowerbot | [slack] <Matt Johnston> kind of blocked at the moment by dram failing memtest | 08:28 |
| openpowerbot | [slack] <Michael Neuling> yeah 😞 | 08:30 |
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