| lkcl | Anton: here's the Phase 2 part, in the SoC HDL (the Chips4Makers JTAG TAP) | 07:31 |
|---|---|---|
| lkcl | https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/jtag.py;h=4b4f17a97d672c3f22b668008a1c058ac2500da6;hb=81194128bb204d8c4c415572533ffc89a3f54648#l75 | 07:31 |
| lkcl | that's it. that's all there is. | 07:31 |
| lkcl | the pinset was read from a JSON file, it's enumerated, it creates the boundary scan JTAG register. | 07:31 |
| lkcl | done. | 07:31 |
| openpowerbot | [slack] <Michael Neuling> @Matt Johnston FWIW I got your tree up and running on my orange crab. getting memory errors also but microwatt/helloworld lives | 09:17 |
| openpowerbot | [slack] <Michael Neuling> some of the organge crab v0.2 makefile stuff could go upstream. some useful stuff in there with the -85k --speed 8 etc | 09:18 |
| openpowerbot | [slack] <Matt Johnston> ah cool. yeah I've been meaning to tidy some of it up to send | 09:18 |
| openpowerbot | [slack] <Matt Johnston> it's very much a WIP branch trying things for myself at the moment | 09:19 |
| openpowerbot | [slack] <Michael Neuling> this helps a bunch on load time and boot time | 09:25 |
| openpowerbot | [slack] <Michael Neuling> ``` microwatt.bit: microwatt_out.config | 09:25 |
| openpowerbot | [slack] <Michael Neuling> - $(ECPPACK) --svf microwatt.svf $< $@ | 09:25 |
| openpowerbot | [slack] <Michael Neuling> + $(ECPPACK) --freq 38.8 --compress --svf microwatt.svf $< $@ | 09:25 |
| openpowerbot | [slack] <Michael Neuling> ``` | 09:25 |
| openpowerbot | [slack] <Matt Johnston> aah, nice | 09:26 |
| openpowerbot | [slack] <Michael Neuling> do we think ignoring timing violations is cauing issues? | 09:26 |
| openpowerbot | [slack] <Michael Neuling> We hve the PLL in there, so we could try going a lot slower | 09:26 |
| openpowerbot | [slack] <Matt Johnston> the memtest fails similarly even if it makes 48mhz timing | 09:27 |
| openpowerbot | [slack] <Michael Neuling> ok | 09:27 |
| openpowerbot | [slack] <Matt Johnston> I did some tests at different speeds with the orangecrab test harness, iirc memtest succeeded at 41mhz upwards, failed at 40mhz | 09:27 |
| openpowerbot | [slack] <Matt Johnston> that is using a litedram+lite* from January though. I tried a bit more recent (march?) and it still succeeded, but when I tried latest litex I had yosys chewing 16GB ram and it OOMed. so maybe an inconclusive test trying to narrow down the differences of microwatt vs that | 09:29 |
| openpowerbot | [slack] <Michael Neuling> ha doh | 09:29 |
| openpowerbot | [slack] <Matt Johnston> I did some tests at different speeds with the orangecrab test harness, memtest succeeded at 41mhz upwards, failed at 40mhz | 09:31 |
| openpowerbot | [slack] <Jeremy Kerr> @Michael Neuling who else has an OC there? | 09:34 |
| openpowerbot | [slack] <Michael Neuling> @Jeremy Kerr @Paul Mackerras does | 10:07 |
| openpowerbot | [slack] <Michael Neuling> anton has one but it's v1 | 10:08 |
| openpowerbot | [slack] <Jeremy Kerr> Anton Blanchard's versions automatically increment | 10:08 |
| lkcl | Matt, Michael: you can't go below about 48 mhz with DDR3 DRAM ICs | 14:00 |
| lkcl | the manufacturing tolerance is around 48 to 55 mhz. | 14:00 |
| lkcl | the DDR3 RAM ICs being used actually have a reported minimum clock rate by the manufacturer of i think 200 mhz. | 14:01 |
| lkcl | Matt: if you have managed to get working at 41 mhz you are extremely lucky. | 14:01 |
| lkcl | cherish that OC for the unique manufacturing tolerances of its DDR3 DRAM IC :) | 14:02 |
| openpowerbot | [slack] <Matt Johnston> yeah. I think I tried microwatt in low 50s too, still no luck. guess could try figure how to get it higher and see how that goes | 14:02 |
| openpowerbot | [slack] <Matt Johnston> the error rate didn't seem to vary much going up or down in the 40s for microwatt, which seems a bit surprising | 14:02 |
| lkcl | you need to get to 55 mhz or above in order to get it to "work for everyone" | 14:03 |
| lkcl | or... | 14:03 |
| openpowerbot | [slack] <Matt Johnston> really need to look at the signals more | 14:03 |
| lkcl | .... just buy a hell of a lot of OCs and test them all individually. | 14:03 |
| lkcl | nextpnr-ecp5's output shows you its timing and the critical paths | 14:04 |
| openpowerbot | [slack] <Matt Johnston> mm. resell them as `--speed 11` | 14:04 |
| openpowerbot | [slack] <Matt Johnston> yep | 14:04 |
| lkcl | lol yeah | 14:04 |
| lkcl | of course, if GHDL obliterates signal names, the output from nextpnr-ecp5 (towards the end of the output) is worse than useless | 14:04 |
| lkcl | because you can't relate the obliterated-signal-names-with-record-information removed | 14:05 |
| lkcl | back to the original VHDL | 14:05 |
| lkcl | sigh | 14:05 |
| openpowerbot | [slack] <Matt Johnston> it's not too bad | 14:05 |
| lkcl | thank goodness for that | 14:05 |
| lkcl | ohhh hang on | 14:05 |
| lkcl | yeahhh | 14:05 |
| lkcl | the DRAM is handled by litex | 14:06 |
| lkcl | litex is in verilog | 14:06 |
| lkcl | verilog has its signals preserved (ish) by nextpnr-ecp5 | 14:06 |
| lkcl | the other thing to watch out for, as the resources of the ECP5 are pushed to the limit, the routing obviously changes | 14:07 |
| lkcl | (to sub-optimal connectivity) | 14:07 |
| openpowerbot | [slack] <Matt Johnston> the vhdl is OK, I think the yosys autoname step might help something? `Info: 0.2 12.5 Source soc0.processor.mmu_0.d_in.err_TRELLIS_FF_Q_LSR_LUT4_Z_D_TRELLIS_FF_DI_Q_LUT4_B_C_LUT4_D_Z_LUT4_Z_D_LUT4_Z_B_LUT4_Z_1_C_LUT4_D_SLICE.F1` | 14:08 |
| lkcl | eurrrrr yukk :) | 14:08 |
| lkcl | well at least you got _some_ useful hierarchy :) | 14:09 |
| lkcl | the rest of that (LUT4_this, MUX_that) will be the FPGA Cell Library replacement step of yosys | 14:10 |
| lkcl | can't do much about that | 14:10 |
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