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| lkcl | <Paul Mackerras> how would that affect the frequency? | 10:07 |
|---|---|---|
| lkcl | PLLs are analog components. | 10:07 |
| lkcl | they will be impacted by current and voltage | 10:07 |
| lkcl | and - this is hilarious - i saw an AI/Evolution FPGA-program-generator paper a few years ago | 10:08 |
| lkcl | they randomly generated programs and, using "evolution", mixed together ones that always passed the test | 10:09 |
| lkcl | you know, the usual "genetic" algorithms for creating programs | 10:09 |
| lkcl | they then looked at what was actually produced. some of the programs evolutionarily-created had gates and FPGA resources linked together in loops that were completely disconnected from all others | 10:10 |
| lkcl | in an "oink" moment the researchers tried removing those disconnected groups... only to find that by doing so that created the *wrong answer* to the test | 10:11 |
| lkcl | in other words, the genetic algorithms had created programs that critically relied on *internal EMF leakage* and analog transmission effects between FPGA resources! | 10:12 |
| lkcl | which is frickin hilarious, and also may help explain why, with a PLL (an analog component that takes time to stabilise its ringing effects), you need to wait for some time. | 10:13 |
| lkcl | :) | 10:13 |
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