| openpowerbot | [slack] <Paul Mackerras> So, what was happening was that whoever wrote the code that set the PLL parameters chose 2MHz for the phase detector frequency, which is out of spec. Consequently the PLL lock indication didn't work and was always 0. So the original author concluded it must be active low and put an inverter on it, meaning that we were starting the microwatt core as soon as the FPGA was configured, while the PLL was s | 03:24 |
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| openpowerbot | [slack] <Jeremy Kerr> @Paul Mackerras you've started hacking on the Orange Crab? how's that going? | 06:42 |
| openpowerbot | [slack] <Paul Mackerras> Hi @jk yes I got an orange crab v0.21 with ecp5 85F and 128MB of DRAM | 06:46 |
| openpowerbot | [slack] <Jeremy Kerr> nice | 06:46 |
| openpowerbot | [slack] <Paul Mackerras> Even though its a -8 speed grade the max clock that nextpnr reports is not as high as with the LFE5UM5G chip on Antpm | 06:48 |
| openpowerbot | [slack] <Paul Mackerras> Even though its a -8 speed grade the max clock that nextpnr reports is not as high as with the LFE5UM5G chip on Anton's card | 06:48 |
| openpowerbot | [slack] <Paul Mackerras> and nextpnr can take up to half an hour to route the chip, which gets tedious | 06:49 |
| openpowerbot | [slack] <Paul Mackerras> At least now simple_random on it gives the same results as on the Arty 🙂 | 06:49 |
| openpowerbot | [slack] <Jeremy Kerr> hm, do you know what the difference is from 0.2 to 0.2.1 ? | 06:50 |
| openpowerbot | [slack] <Paul Mackerras> the size of the FPGA? I'm not really sure | 06:50 |
| openpowerbot | [slack] <Paul Mackerras> also it has a type-C USB rather than a micro type-B | 06:50 |
| openpowerbot | [slack] <Jeremy Kerr> looks like the 0.2 didn't have an 85F + 128MB option | 06:50 |
| openpowerbot | [slack] <Jeremy Kerr> (just 85F + 512) | 06:51 |
| openpowerbot | [slack] <Matt Johnston> pretty much identical apart from 0.2.1 doesn't have a jtag header and the usb-c | 06:51 |
| openpowerbot | [slack] <Matt Johnston> pretty much identical apart from 0.2.1 doesn't have a jtag header and 0.2.1 has usb-c | 06:52 |
| openpowerbot | [slack] <Paul Mackerras> actually the DRAM is 1Gb (128GB) | 06:55 |
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| lkcl | Paul: ooo doh. good find. does that propagate right the way through all other ECP5 boards? (as in: was it an issue with a base class covering *all* ECP5 boards, VERSA_ECP5, ULX3S etc.)? | 10:12 |
| openpowerbot | [slack] <Paul Mackerras> lkcl, currently we only have targets in the Makefile for ECP5-EVN and Orange Crab, and the fix affects both of those | 23:10 |
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