| *** lkcl <lkcl!lkcl@we.will.rock.you.bnc4you.xyz> has quit IRC | 00:28 | |
| openpowerbot | [slack] <Matt Johnston> with default `LINE_SIZE` 128 I see bad stores at 128 byte intervals. reducing `LINE_SIZE` to 32 or 16 I see bad stores at 64 byte intervals. so it seems to be related to litedram or the wrapper | 00:50 |
|---|---|---|
| openpowerbot | [slack] <Jeremy Kerr> @Matt Johnston what do you mean by intervals there? sucessive loads would succeed up to the next $interval offset? | 01:24 |
| openpowerbot | [slack] <Matt Johnston> I'm doing load/store `0x40500000`, `0x40500001` , `0x40500002` etc. `0x40500000` doesn't store, then it's correct until `0x40500040` fails, then `0x40500080` fails | 01:26 |
| openpowerbot | [slack] <Matt Johnston> (that's the 64 byte interval failing) | 01:26 |
| openpowerbot | [slack] <Matt Johnston> I'm doing store/load `0x40500000`, `0x40500001` , `0x40500002` etc. `0x40500000` doesn't store, then it's correct until `0x40500040` fails, then `0x40500080` fails | 01:28 |
| openpowerbot | [slack] <Jeremy Kerr> ok, makes sense | 01:30 |
| *** lkcl <lkcl!lkcl@we.will.rock.you.bnc4you.xyz> has joined #microwatt | 02:36 | |
| *** toshywoshy <toshywoshy!~toshywosh@ptr-377wf33o3bnthuddmycb.18120a2.ip6.access.telenet.be> has quit IRC | 04:01 | |
| *** toshywoshy <toshywoshy!~toshywosh@ptr-377wf33o3bnthuddmycb.18120a2.ip6.access.telenet.be> has joined #microwatt | 04:01 | |
| *** openpowerbot <openpowerbot!~openpower@94-226-186-169.access.telenet.be> has quit IRC | 04:02 | |
| *** openpowerbot <openpowerbot!~openpower@94-226-186-169.access.telenet.be> has joined #microwatt | 04:03 | |
| openpowerbot | [slack] <Paul Mackerras> @Matt Johnston do you have a little stand-alone test case that shows the problem, which we could run in core_tb for instance? | 06:25 |
| openpowerbot | [slack] <Matt Johnston> yep, let me just tidy it up | 06:25 |
| openpowerbot | [slack] <Matt Johnston> @Paul Mackerras https://matt.ucc.asn.au/files/dud_store-2c713cd5a.tar.gz or https://github.com/mkj/microwatt/tree/matt/dud_store/dud_store | 06:56 |
| openpowerbot | [slack] <Matt Johnston> https://github.com/mkj/microwatt/blob/matt/dud_store/dud_store/dudstdio_asm.s#L41 is the test | 06:57 |
| openpowerbot | [slack] <Matt Johnston> for reference I get incorrect output of | 07:01 |
| openpowerbot | [slack] <Matt Johnston> ```+99-+00-+89-+00-+00-+01-+01-+02-+02-+03-+03-+04-+04-+05-+05-+06-+06-+07-+07-+08-+08-+09-+09-+0a-+0a-+0b-+0b-+0c-+0c-+0d-+0d-+0e-+0e-+0f-+0f- | 07:01 |
| openpowerbot | [slack] <Matt Johnston> ^here | 07:01 |
| openpowerbot | [slack] <Matt Johnston> +10-+10-+11-+11-+12-+12-+13-+13-+14-+14-+15-+15-+16-+16-+17-+17-+18-+18-+19-+19-+1a-+1a-+1b-+1b-+1c-+1c-+1d-+1d-+1e-+1e-+1f-+1f-+20-+20-+21- | 07:01 |
| openpowerbot | [slack] <Matt Johnston> +21-+22-+22-+23-+23-+24-+24-+25-+25-+26-+26-+27-+27-+28-+28-+29-+29-+2a-+2a-+2b-+2b-+2c-+2c-+2d-+2d-+2e-+2e-+2f-+2f-+30-+30-+31-+31-+32-+32- | 07:01 |
| openpowerbot | [slack] <Matt Johnston> +33-+33-+34-+34-+35-+35-+36-+36-+37-+37-+38-+38-+39-+39-+3a-+3a-+3b-+3b-+3c-+3c-+3d-+3d-+3e-+3e-+3f-+3f-+40-+00-+41-+41-+42-+42-+43-+43 ....etc | 07:01 |
| openpowerbot | [slack] <Matt Johnston> ^here``` | 07:01 |
| openpowerbot | [mattermost] <lkcl> matt: did you check that microwatt load/store itself is not the source of the problem by trying with l2_size = 0? | 09:39 |
| openpowerbot | [mattermost] <lkcl> that will eliminate the L2 cache entirely in litex | 09:40 |
| openpowerbot | [mattermost] <lkcl> and, running under sim.py will eliminate litedram. | 09:40 |
| openpowerbot | [slack] <Matt Johnston> lkcl: it's using microwatt's litedram-wrapper-l2, not a simple way to avoid that | 09:41 |
| openpowerbot | [mattermost] <lkcl> otherwise, of course, you have 4 unknowns, any one of which could be the contributor... | 09:41 |
| openpowerbot | [mattermost] <lkcl> ah | 09:41 |
| openpowerbot | [mattermost] <lkcl> then you may be interested to know that the setup in libre-soc completely bypassed that. let me find the source... | 09:41 |
| openpowerbot | [mattermost] <lkcl> https://git.libre-soc.org/?p=libresoc-litex.git;a=blob;f=sim.py;hb=HEAD | 09:42 |
| openpowerbot | [mattermost] <lkcl> https://git.libre-soc.org/?p=libresoc-litex.git;a=blob;f=microwatt/core.py;hb=HEAD | 09:42 |
| openpowerbot | [mattermost] <lkcl> that's an older version, may (almost certainly will) need updating | 09:43 |
| openpowerbot | [mattermost] <lkcl> you should however be able to use it to *directly* connect the microwatt core to a (simulated) memory, no L2 cache | 09:43 |
| openpowerbot | [mattermost] <lkcl> which will eliminate 2 out of 4 of the unknowns. | 09:44 |
| openpowerbot | [mattermost] <lkcl> hth | 09:44 |
| openpowerbot | [slack] <Matt Johnston> hm | 09:44 |
| openpowerbot | [slack] <Matt Johnston> I'm not quite sure where the size of 64 bytes is coming from. seems like it's probably related to litedram parameters | 09:45 |
| openpowerbot | [mattermost] <lkcl> if Paul's fixed the Wishbone issues (3 extra zeros) then at lines 75 and 87 you'll need to remove the Signal(3) | 09:45 |
| openpowerbot | [mattermost] <lkcl> and bump up the adr_width at lines 51 and 52 to 32-bit | 09:46 |
| openpowerbot | [slack] <Matt Johnston> I'll have a look, thanks | 09:47 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> 64 bytes smells like litedram | 19:55 |
Generated by irclog2html.py 2.17.1 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!