| openpowerbot | [slack] <Paul Mackerras> @Matt Johnston around? I am having trouble building your dud_store branch for orange crab | 02:45 |
|---|---|---|
| openpowerbot | [slack] <Matt Johnston> yep | 02:45 |
| openpowerbot | [slack] <Paul Mackerras> Doing | 02:45 |
| openpowerbot | [slack] <Paul Mackerras> ```$ PODMAN=1 make microwatt.bit``` | 02:45 |
| openpowerbot | [slack] <Paul Mackerras> gives | 02:45 |
| openpowerbot | [slack] <Paul Mackerras> ```-- Parsing `valentyusb/generated/orangecrab-85-0.2/gateware/valentyusb.v' using frontend `verilog' -- | 02:45 |
| openpowerbot | [slack] <Paul Mackerras> | 02:45 |
| openpowerbot | [slack] <Paul Mackerras> 11. Executing Verilog-2005 frontend: valentyusb/generated/orangecrab-85-0.2/gateware/valentyusb.v | 02:45 |
| openpowerbot | [slack] <Paul Mackerras> valentyusb/generated/orangecrab-85-0.2/gateware/valentyusb.v:0: ERROR: Can not open file `out_buffer.init` for \$readmemh. | 02:45 |
| openpowerbot | [slack] <Paul Mackerras> make: *** [Makefile:239: microwatt.json] Error 1``` | 02:45 |
| openpowerbot | [slack] <Paul Mackerras> What am I missing? | 02:45 |
| openpowerbot | [slack] <Matt Johnston> let me see. I've been using oss-cad-suite | 02:46 |
| openpowerbot | [slack] <Matt Johnston> let me see. I've been using oss-cad-suite rather than docker | 02:46 |
| openpowerbot | [slack] <Matt Johnston> ah I'd missed committing some valentyusb files, I've pushed them now | 02:48 |
| openpowerbot | [slack] <Matt Johnston> note that I have valentyusb disabled in top-orangecrab at the moment | 02:48 |
| openpowerbot | [slack] <Paul Mackerras> What is the expected output? I ran it in core_tb and it just printed a whole bunch of hex numbers | 02:49 |
| openpowerbot | [slack] <Matt Johnston> it should print each number twice, the byte being written then the byte read back | 02:49 |
| openpowerbot | [slack] <Matt Johnston> (apart from the first 99) | 02:49 |
| openpowerbot | [slack] <Matt Johnston> the error is that offset 40 for example will read back 00 rather than 40 | 02:50 |
| openpowerbot | [slack] <Paul Mackerras> and on the OC do I use the i/o pins for the uart as before, or do we get a usb uart now? | 02:50 |
| openpowerbot | [slack] <Matt Johnston> it's using IO for uart | 02:50 |
| openpowerbot | [slack] <Matt Johnston> 16550 uart0 | 02:50 |
| openpowerbot | [slack] <Paul Mackerras> cool | 02:50 |
| openpowerbot | [slack] <Paul Mackerras> what does valentyusb implement then? | 02:50 |
| openpowerbot | [slack] <Matt Johnston> liteuart | 02:50 |
| openpowerbot | [slack] <Matt Johnston> currently I have it on the same address as uart0 but think that's a mistake, will move it elsewhere | 02:51 |
| openpowerbot | [slack] <Paul Mackerras> hmmm, it's a pity we have to have yet another register layout for a uart... | 02:51 |
| openpowerbot | [slack] <Matt Johnston> mm yeah. maybe I could hook valentyusb up as a phy for the current 16550 or something | 02:52 |
| openpowerbot | [slack] <Matt Johnston> or once Linux is going hopefully use it with USB gadget drivers | 02:53 |
| openpowerbot | [slack] <Matt Johnston> (not sure how that'd work for Linux console though) | 02:53 |
| openpowerbot | [slack] <Paul Mackerras> Do we have any way to hook up Ben's DMI stuff to jtag on the OC? | 02:55 |
| openpowerbot | [slack] <Matt Johnston> not at the moment | 02:56 |
| openpowerbot | [slack] <Matt Johnston> there's a JTAGG component that should be able to do it | 02:57 |
| openpowerbot | [slack] <Matt Johnston> there's a JTAGG component that should be able to do it. https://github.com/tomverbeure/ecp5_jtag | 03:01 |
| openpowerbot | [slack] <Matt Johnston> there's a JTAGG component that should be able to do it. https://github.com/tomverbeure/ecp5_jtag | 03:01 |
| openpowerbot | [slack] <Matt Johnston> there's a JTAGG component that should be able to do it. https://github.com/tomverbeure/ecp5_jtag | 03:02 |
| openpowerbot | [slack] <Paul Mackerras> hmmm on my OC, the LED goes white but I don't see anything on the serial port | 03:09 |
| openpowerbot | [slack] <Matt Johnston> it works with microwatt master branch? | 03:14 |
| openpowerbot | [slack] <Paul Mackerras> yes | 03:15 |
| openpowerbot | [slack] <Paul Mackerras> hmm that would have built with hello_world as the RAM_INIT_FILE... I should override that. Still, it should have printed the lightbulb ascii art. | 03:16 |
| openpowerbot | [slack] <Matt Johnston> yeah, it should run the dram init | 03:16 |
| openpowerbot | [slack] <Matt Johnston> let me try a clean docker build here | 03:17 |
| openpowerbot | [slack] <Paul Mackerras> does the led colour indicate anything about the dram init progress? | 03:21 |
| openpowerbot | [slack] <Matt Johnston> I don't think so. I haven't really done anything with the leds, though I'm setting the dram init done flag early on becaues otherwise litedram was stalling in memtest. https://github.com/mkj/litex/commit/9a1990b29fbcd1432215503740958e577fd814fa | 03:24 |
| openpowerbot | [slack] <Matt Johnston> mm, my docker build doesn't work either, trying a clean non-docker build | 04:07 |
| openpowerbot | [slack] <Matt Johnston> @Paul Mackerras ah sorry, I had missed committing generated litedram when switching back to uart0, I've force pushed that branch and it should work now | 06:14 |
| openpowerbot | [slack] <Paul Mackerras> ok thanks | 06:15 |
| openpowerbot | [slack] <Paul Mackerras> @Matt Johnston Your tree built for the arty A7 running dud_store doesn't show the problem, FWIW | 11:22 |
| openpowerbot | [mattermost] <lkcl> Matt: that JTAGG hooks into existing shift-registers (not really designed precisely for any particular job) which are hard-wired into the JTAG TAP silicon of the ECP5. | 16:15 |
| openpowerbot | [mattermost] <lkcl> the approach in libre-soc that we took summarises as, "nuts to that" :) | 16:15 |
| openpowerbot | [mattermost] <lkcl> we instead used 4 GPIOs and a full-on JTAG-TAP interface written by Staf Verhaegen - c4m-jtag | 16:16 |
| openpowerbot | [mattermost] <lkcl> then documented how to use it / connect to it https://libre-soc.org/HDL_workflow/ECP5_FPGA/ | 16:16 |
| openpowerbot | [mattermost] <lkcl> Staf's JTAG TAP - initially really designed for ASICs - works perfectly well on FPGAs https://gitlab.com/Chips4Makers/c4m-jtag/ | 16:17 |
| openpowerbot | [mattermost] <lkcl> you're then not at the mercy of however long Lattice decided that however little shift registers should be... you get the idea | 16:17 |
| openpowerbot | [mattermost] <lkcl> and aren't working at a manufacturer-defined level rather than "the actual real JTAG standard" level | 16:18 |
| openpowerbot | [mattermost] <lkcl> i could be wrong: you *might* iirc actually be able to hook into the shift/update cycle of JTAG, which would allow you to define your *own* data and control shift registers | 16:19 |
| openpowerbot | [mattermost] <lkcl> the only downside of doing JTAG entirely yourself (using c4m-jtag) is that you of course have to connect a completely separate JTAG-USB to the ECP5. | 16:20 |
| openpowerbot | [mattermost] <lkcl> and now you have _two_ possible ground-loop opportunitites :) | 16:20 |
| openpowerbot | [slack] <mithro> This isn't a microwatt question, but I thought people here might know -- How does one boot / setup a system so that kernel messages / output / console goes both to a serial console + graphics display console? | 23:09 |
| openpowerbot | [slack] <Peter Gielda> As far as I remember you set bootargs to both to sth like console=ttyS0 and console=tty1. You specify it twice | 23:26 |
| openpowerbot | [slack] <Jeremy Kerr> yep, that's it. | 23:54 |
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