ULX3S JTAG Connection with STLINKV2

Cross referenced with:

https://bugs.libre-soc.org/show_bug.cgi?id=517

http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/000873.html

Original Instructions

See https://bugs.libre-soc.org/show_bug.cgi?id=517#c0

Checklist based on above

  • For god's sake make sure you get this right, TRIPLE check everything.

  • DO make sure to only drive an input as an input, and to only drive an output as an output.

  • DO make sure to only wire up 5.0V to 5.0V and to only wire up GND to GND with the jumper-cables.

  • DO make sure that before even thinking of uploading to and powering up the FPGA that everything has been THOROUGHLY triple-checked.

If you violate any of the above stated hard-and-fast rules you will end up learning the hard way by DESTROYING the FPGA.

To start we have to ensure we have a safe set up.

  • Ensure power is disconnected from FPGA
  • Ensure STLINKV2 USB is disconnected
  • Ensure FPGA USB is disconnected
Done? Checklist Step
Review the STLINKv2 Connector diagram and table
Review the connections table for your model of fpga
Make sure the orientation of your FPGA board and your STLINKv2 are the same as the images and diagrams on this page
Wire each of the coloured jumper cables to the corresponding pins on the FPGA and the STLINKv2 according to the diagrams, tables, and images on this page. Below are separate checklist for each model of FPGA

ADD TABLE CONNECTING STLINK MALE-TO-FEMALE JUMPERS HERE. START WITH DUPLICATE COPY OF ULX3S TABLE AND REMOVE "(ULX3S PIN #N)"

Follow this section if you have the ULX3S FPGA:

Done? Checklist Step
Wire the RED jumper cable to (ULX3S pin #2) then wire it to (STLINKv2 pin #2), this will serve as the Voltage Reference signal (VREF)

REMOVE MENTION OF STLINK FROM HERE. REQUIRE JUMPER TO BE FEMALETOFEMALE. REPEAT FOR ALL TABLE ENTRIES

| | Wire the BLACK jumper cable to (ULX3S pin #4) then wire it to (STLINKv2 pin #4), this will serve as the Ground signal (GND) | | | Wire the GREEN jumper cable to (ULX3S pin #5) then wire it to (STLINKv2 pin #5), this will serve as the Test Data In signal (TDI) | | | Wire the BLUE jumper cable to (ULX3S pin #6) then wire it to (STLINKv2 pin #7), this will serve as the Test Mode Select signal (TMS) | | | Wire the WHITE jumper cable to (ULX3S pin #7) then wire it to (STLINKv2 pin #9), this will serve as the Test Clock signal (TCK) | | | Wire the YELLOW jumper cable to (ULX3S pin #8) then wire it to (STLINKv2 pin #13), this will serve as the Test Data Out signal (TDO) |

Follow this section if you have the Versa ECP5 FPGA:

Done? Checklist Step
Wire the RED jumper cable to (X3 pin #39) then wire it to (STLINKv2 pin #2), this will serve as the Voltage Reference signal (VREF)
Wire the BLACK jumper cable to (X3 pin #1) then wire it to (STLINKv2 pin #4), this will serve as the Ground signal (GND)
Wire the GREEN jumper cable to (X3 pin #4) then wire it to (STLINKv2 pin #5), this will serve as the Test Data In signal (TDI)
Wire the BLUE jumper cable to (X3 pin #5) then wire it to (STLINKv2 pin #7), this will serve as the Test Mode Select signal (TMS)
Wire the WHITE jumper cable to (X3 pin #6) then wire it to (STLINKv2 pin #9), this will serve as the Test Clock signal (TCK)
Wire the YELLOW jumper cable to (X3 pin #7) then wire it to (STLINKv2 pin #13), this will serve as the Test Data Out signal (TDO)

Final steps for both FPGA boards:

Done? Checklist Step
Check each jumper wire connection between the corresponding pins on the FPGA and the STLINKv2 THREE times
lckl check for ground loops?

Connecting the dots:

Accurate render of board for reference https://github.com/emard/ulx3s/blob/master/pic/ulx3st.jpg

STLINKV2 Pins and JTAG signals schematic/user guide https://www.st.com/resource/en/user_manual/dm00026748-stlinkv2-incircuit-debuggerprogrammer-for-stm8-and-stm32-stmicroelectronics.pdf

Litex platform file https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/ulx3s.py

("gpio", 0,
    Subsignal"p", Pins("B11")),
    Subsignal("n", Pins("C11")),
    IOStandard("LVCMOS33")
),
("gpio", 1,
    Subsignal("p", Pins("A10")),
    Subsignal("n", Pins("A11")),
    IOStandard("LVCMOS33")
),

ULX3S FPGA constraints file https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf#L341-342

LOCATE COMP "gp[0]" SITE "B11"; # J1_5+  GP0 PCLK
LOCATE COMP "gn[0]" SITE "C11"; # J1_5-  GN0 PCLK
LOCATE COMP "gp[1]" SITE "A10"; # J1_7+  GP1 PCLK
LOCATE COMP "gn[1]" SITE "A11"; # J1_7-  GN1 PCLK

ULX3S FPGA Schematic https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf

J1 J2 PIN number 1-40 is for FEMALE 90° ANGLED header.
For MALE VERTICAL header, SWAP EVEN and ODD pin numbers.

                    J1

 Label  [GP{x}]|PCB pin label|[GN{x}] Label
           (Pin count +)(Pin count -)
_________________V__________V________________
 IO VOLT REF 3V3 2  |3.3V|  1  NOT CONNECTED
           [GND] 4  | -| |  3  NOT CONNECTED
PCLKT0_0   [GP0] 6  |  0 |  5  [GN0] PCLKC0_0
PCLKT0_1   [GP1] 8  |  1 |  7  [GN1] PCLKC0_1 


GP,GN 0-7 single-ended connected to Bank0
GP,GN 8-13 differential bidirectional connected to BANK7

Connecting all the dots:

Board pin # (count) | Board pin label # | FPGA IO PAD | GPIO # (n/p) |   Label  |
      5 (J1_5-)     |         0         |      C11    |    gn[0]     | PCLKC0_0 |
      6 (J1_5+)     |         0         |      B11    |    gp[0]     | PCLKT0_0 |
      7 (J1_7-)     |         1         |      A11    |    gn[1]     | PCLKC0_1 |
      8 (J1_7+)     |         1         |      A10    |    gp[1]     | PCLKT0_1 |

As noted in the schematic pins GP,GN 0-7 are single ended non-differential pairs, whereas pins GP,GN 8-13 I haven't mapped out here as they are bidirectional differential pairs.

Proposed FPGA External Pin to STLINK JTAG pin connections:

   all pin #'s have headers pins on the fpga unless denoted as (no header)
 ______________________________________________________________________________
|             | board |             |             |                |           |
|             | label |             |             |STLINKV2  JTAG  |           |
|    pin #    |   #   | FPGA IO PAD |GPIO # (n/p) | Pin #  (Signal)|Wire Colour|
|_____________|_______|_____________|_____________|________________|___________|
|1 (no header)|  3.3v |NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
|2            |  3.3v | IO VOLT REF | IO VOLT REF |    2 (MCU VDD) |    Red    |
|3 (no header)|-|(GND)|NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
|4            |-|(GND)|    NONE     |     GND     |    4 (GND)     |   Black   |
|5 (J1_5-)    |   0   |     C11     |    gn[0]    |    5 (JTDI)    |   Green   |
|6 (J1_5+)    |   0   |     B11     |    gp[0]    |    7 (JTMS)    |   Blue    |
|7 (J1_7-)    |   1   |     A11     |    gn[1]    |    9 (JTCK)    |   White   |
|8 (J1_7+)    |   1   |     A10     |    gp[1]    |   13 (JTDO)    |   Yellow  |
|_____________|_______|_____________|_____________|________________|___________|

Complete diagram:

Pins intentionally have no header or are not connected to the STLINKVT are marked
and therefore have no value are marked with 'NOT'

(ST# JTAG) = (STLINKV2 pin #   JTAG signal name)


                             J1
            Wire                             Wire
           Colour [GP{x}]|PCB label|[GN{x}] Colour
(ST# JTAG)        (Pin count +)(Pin count -)      (ST# JTAG)
 ________________________V__________V_________________________
|                                                             |
|( 2 JVDD) red    [VREF] 2  |3.3V|  1   NOT   NOT    NOT      |
|( 4 JGND) black   [GND] 4  | -| |  3   NOT   NOT    NOT      |
|( 7 JTMS) blue    [GP0] 6  |  0 |  5  [GN0] green (5 JTDI)   |
|(13 JTDO) yellow  [GP1] 8  |  1 |  7  [GN1] white (9 JTCK)   |
|_____________________________________________________________|

Images of wires on FPGA and on STLINKV2

Image of JTAG jumper wire connections on ULX3S FPGA side

Image of JTAG jumper wire connections on STLINKV2 side

(same orientation as JTAG pinout documentation)

Image of JTAG jumper wire connections on STLINKV2 side

(opposite orientation as JTAG pinout documentation,

same orientation as 'ST' text on STLINKV2 device)

STLinkV2 connector

VERSA ECP5 Connections

Table of connections:

X3 pin # FPGA IO PAD STLinkv2 Wire Colour
39 +3.3V 3.3V supply 2 (MCU VDD) Red
1 GND GND 4 (GND) Black
4 IO29 B19 5 (TDI) Green
5 IO30 B12 7 (TMS) Blue
6 IO31 B9 9 (TCK) White
7 IO32 E6 13 (TDO) Yellow