ULX3S JTAG Connection with STLINKV2

Cross referenced with:

https://bugs.libre-soc.org/show_bug.cgi?id=517

http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/000873.html

Original Instructions

See https://bugs.libre-soc.org/show_bug.cgi?id=517#c0

Checklist based on above

  • For god's sake make sure you get this right, TRIPLE check everything.

  • DO make sure to only drive an input as an input, and to only drive an output as an output.

  • DO make sure to only wire up 5.0V to 5.0V and to only wire up GND to GND with the jumper-cables.

  • DO make sure that before even thinking of uploading to and powering up the FPGA that everything has been THOROUGHLY triple-checked.

If you violate any of the above stated hard-and-fast rules you will end up learning the hard way by DESTROYING the FPGA.

To start we have to ensure we have a safe set up.

Checklist Step
Ensure power is disconnected from FPGA
Ensure STLINKV2 USB is disconnected
Ensure FPGA USB is disconnected

Now lets review all of the relevant material on this page before we begin the wiring process.

Checklist Step
Review the STLINKv2 Connector diagram and table
Review the connections table for your model of fpga
Ensure the orientation of the FPGA and STLINKv2 match that of the images and diagrams on this page

Next we will wire up the STLINKv2 and our FPGA in three separate stages.

  • First we will attach the FEMALE end of a FEMALE-TO-MALE (FTM) jumper cable to each necessary header pin on the STLINKv2.

  • Then we will attach one end of a FEMALE-TO-FEMALE (FTF) cable to each male header pin on the FPGA.

  • Finally, we will connect the wires from the STLINKv2 to the wires from the FPGA by matching the colours of the wires.

This way you do not lose the connections when you want to disconnect and store the two devices. We are using FEMALE-TO-FEMALE jumper cables on the male header pins of the FPGA so that the wires do not randomly damage the bare PCB due to a short.

We will wire each of the pins on the the STLINKv2 according to the diagrams, tables, and images on this page.

Action Colour Pin # Pin Name
Attach FTM Red 2 VREF
Attach FTM Black 4 GND
Attach FTM Green 5 TDI
Attach FTM Blue 7 TMS
Attach FTM White 9 TCK
Attach FTM Yellow 13 TDO

Next, we will wire each of the pins on the the FPGA according to the diagrams, tables, and images on this page.

Follow this section if you have the ULX3S FPGA:

Action Colour Pin # Pin Name
Attach FTF Red 2 VREF
Attach FTF Black 4 GND
Attach FTF Green 5 TDI
Attach FTF Blue 6 TMS
Attach FTF White 7 TCK
Attach FTF Yellow 8 TDO

Follow this section if you have the Versa ECP5 FPGA:

Action Colour X3 Pin # Pin Name
Attach FTF Red 39 VREF
Attach FTF Black 1 GND
Attach FTF Green 4 TDI
Attach FTF Blue 5 TMS
Attach FTF White 6 TCK
Attach FTF Yellow 7 TDO

Final steps for both FPGA boards:

Checklist Step
Check each jumper wire connection between the corresponding pins on the FPGA and the STLINKv2 THREE times
lckl check for ground loops?

Finally, we will connect the jumper cables of the same colour from STLINKv2 and the FPGA.

Checklist Step
Attach the ends of the RED jumper cables
Attach the ends of the BLACK jumper cables
Attach the ends of the GREEN jumper cables
Attach the ends of the BLUE jumper cables
Attach the ends of the WHITE jumper cables
Attach the ends of the YELLOW jumper cables

Connecting the dots:

Accurate render of board for reference https://github.com/emard/ulx3s/blob/master/pic/ulx3st.jpg

STLINKV2 Pins and JTAG signals schematic/user guide https://www.st.com/resource/en/user_manual/dm00026748-stlinkv2-incircuit-debuggerprogrammer-for-stm8-and-stm32-stmicroelectronics.pdf

Litex platform file https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/ulx3s.py

("gpio", 0,
    Subsignal"p", Pins("B11")),
    Subsignal("n", Pins("C11")),
    IOStandard("LVCMOS33")
),
("gpio", 1,
    Subsignal("p", Pins("A10")),
    Subsignal("n", Pins("A11")),
    IOStandard("LVCMOS33")
),

ULX3S FPGA constraints file https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf#L341-342

LOCATE COMP "gp[0]" SITE "B11"; # J1_5+  GP0 PCLK
LOCATE COMP "gn[0]" SITE "C11"; # J1_5-  GN0 PCLK
LOCATE COMP "gp[1]" SITE "A10"; # J1_7+  GP1 PCLK
LOCATE COMP "gn[1]" SITE "A11"; # J1_7-  GN1 PCLK

ULX3S FPGA Schematic https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf

J1 J2 PIN number 1-40 is for FEMALE 90° ANGLED header.
For MALE VERTICAL header, SWAP EVEN and ODD pin numbers.

                    J1

 Label  [GP{x}]|PCB pin label|[GN{x}] Label
           (Pin count +)(Pin count -)
_________________V__________V________________
 IO VOLT REF 3V3 2  |3.3V|  1  NOT CONNECTED
           [GND] 4  | -| |  3  NOT CONNECTED
PCLKT0_0   [GP0] 6  |  0 |  5  [GN0] PCLKC0_0
PCLKT0_1   [GP1] 8  |  1 |  7  [GN1] PCLKC0_1 


GP,GN 0-7 single-ended connected to Bank0
GP,GN 8-13 differential bidirectional connected to BANK7

Connecting all the dots:

Board pin # (count) | Board pin label # | FPGA IO PAD | GPIO # (n/p) |   Label  |
      5 (J1_5-)     |         0         |      C11    |    gn[0]     | PCLKC0_0 |
      6 (J1_5+)     |         0         |      B11    |    gp[0]     | PCLKT0_0 |
      7 (J1_7-)     |         1         |      A11    |    gn[1]     | PCLKC0_1 |
      8 (J1_7+)     |         1         |      A10    |    gp[1]     | PCLKT0_1 |

As noted in the schematic pins GP,GN 0-7 are single ended non-differential pairs, whereas pins GP,GN 8-13 I haven't mapped out here as they are bidirectional differential pairs.

Proposed FPGA External Pin to STLINK JTAG pin connections:

   all pin #'s have headers pins on the fpga unless denoted as (no header)
 ______________________________________________________________________________
|             | board |             |             |                |           |
|             | label |             |             |STLINKV2  JTAG  |           |
|    pin #    |   #   | FPGA IO PAD |GPIO # (n/p) | Pin #  (Signal)|Wire Colour|
|_____________|_______|_____________|_____________|________________|___________|
|1 (no header)|  3.3v |NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
|2            |  3.3v | IO VOLT REF | IO VOLT REF |    2 (MCU VDD) |    Red    |
|3 (no header)|-|(GND)|NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
|4            |-|(GND)|    NONE     |     GND     |    4 (GND)     |   Black   |
|5 (J1_5-)    |   0   |     C11     |    gn[0]    |    5 (JTDI)    |   Green   |
|6 (J1_5+)    |   0   |     B11     |    gp[0]    |    7 (JTMS)    |   Blue    |
|7 (J1_7-)    |   1   |     A11     |    gn[1]    |    9 (JTCK)    |   White   |
|8 (J1_7+)    |   1   |     A10     |    gp[1]    |   13 (JTDO)    |   Yellow  |
|_____________|_______|_____________|_____________|________________|___________|

Complete diagram:

Pins intentionally have no header or are not connected to the STLINKVT are marked
and therefore have no value are marked with 'NOT'

(ST# JTAG) = (STLINKV2 pin #   JTAG signal name)


                             J1
            Wire                             Wire
           Colour [GP{x}]|PCB label|[GN{x}] Colour
(ST# JTAG)        (Pin count +)(Pin count -)      (ST# JTAG)
 ________________________V__________V_________________________
|                                                             |
|( 2 JVDD) red    [VREF] 2  |3.3V|  1   NOT   NOT    NOT      |
|( 4 JGND) black   [GND] 4  | -| |  3   NOT   NOT    NOT      |
|( 7 JTMS) blue    [GP0] 6  |  0 |  5  [GN0] green (5 JTDI)   |
|(13 JTDO) yellow  [GP1] 8  |  1 |  7  [GN1] white (9 JTCK)   |
|_____________________________________________________________|

Images of wires on FPGA and on STLINKV2

Image of JTAG jumper wire connections on ULX3S FPGA side

Image of JTAG jumper wire connections on STLINKV2 side

(same orientation as JTAG pinout documentation)

Image of JTAG jumper wire connections on STLINKV2 side

(opposite orientation as JTAG pinout documentation,

same orientation as 'ST' text on STLINKV2 device)

STLinkV2 connector

VERSA ECP5 Connections

Table of connections:

X3 pin # FPGA IO PAD STLinkv2 Wire Colour
39 +3.3V 3.3V supply 2 (MCU VDD) Red
1 GND GND 4 (GND) Black
4 IO29 B19 5 (TDI) Green
5 IO30 B12 7 (TMS) Blue
6 IO31 B9 9 (TCK) White
7 IO32 E6 13 (TDO) Yellow