Simple-V Vectorisation for the OpenPOWER ISA

Fundamental design principles:

  • Simplicity of introduction and implementation on the existing OpenPOWER ISA
  • Effectively a hardware for-loop, pausing PC, issuing multiple scalar operations
  • Augments ("tags") existing instructions, providing Vectorisation "context" rather than adding new ones.

Advantages of these design principles:

  • It is therefore easy to create a first (and sometimes only) implementation as literally a for-loop in hardware, simulators, and compilers.
  • More complex HDL can be done by repeating existing scalar ALUs and pipelines as blocks.
  • As (mostly) a high-level "context" that does not (significantly) deviate from scalar OpenPOWER ISA it is minimally-disruptive and consequently stands a reasonable chance of broad community adoption and acceptance

Pages being developed and examples