Note on considered alternative naming schemes: we decided to switch to using the reduced mnemonic naming scheme (over some people's objections) since it would be 5 instructions instead of dozens, though we did consider trying to match PowerISA's existing naming scheme for the instructions rather than only for the instruction aliases. https://bugs.libresoc.org/show_bug.cgi?id=1015#c7
FPRtoGPR and GPRtoFPR
TODO special constants instruction (e, tau/N, ln 2, sqrt 2, etc.)  exclude any constants available through fmvis
Draft Status under development, for submission as an RFC
Links:
 https://bugs.libresoc.org/show_bug.cgi?id=650
 https://bugs.libresoc.org/show_bug.cgi?id=230#c71
 https://bugs.libresoc.org/show_bug.cgi?id=230#c74
 https://bugs.libresoc.org/show_bug.cgi?id=230#c76
 https://bugs.libresoc.org/show_bug.cgi?id=887 fmvis
 https://bugs.libresoc.org/show_bug.cgi?id=1015 intfp RFC
 appendix
 ls002.fmi 
fmvis
andfishmv
External RFC Formal Submission  ls006.fpintmv  intfpmv External RFC Formal Submission
Trademarks:
 Rust is a Trademark of the Rust Foundation
 Java and JavaScript are Trademarks of Oracle
 LLVM is a Trademark of the LLVM Foundation
 SPIRV is a Trademark of the Khronos Group
 OpenCL is a Trademark of Apple, Inc.
Referring to these Trademarks within this document is by necessity, in order to put the semantics of each language into context, and is considered "fair use" under Trademark Law.
Introduction:
Highperformance CPU/GPU software needs to often convert between integers and floatingpoint, therefore fast conversion/datamovement instructions are needed. Also given that initialisation of floats tends to take up considerable space (even to just load 0.0) the inclusion of two compact format float immediate instructions is up for consideration using 16bit immediates. BF16 is one of the formats: a second instruction allows a full accuracy FP32 to be constructed.
LibreSOC will be compliant with the Scalar FloatingPoint Subset (SFFS) i.e. is not implementing VMX/VSX, and with its focus on modern 3D GPU hybrid workloads represents an important new potential usecase for OpenPOWER.
Prior to the formation of the Compliancy Levels first introduced in v3.0C and v3.1 the progressive historic development of the Scalar parts of the Power ISA assumed that VSX would always be there to complement it. However With VMX/VSX not available in the newlyintroduced SFFS Compliancy Level, the existing nonVSX conversion/datamovement instructions require a Vector of load/store instructions (slow and expensive) to transfer data between the FPRs and the GPRs. For a modern 3D GPU this kills any possibility of a competitive edge. Also, because SimpleV needs efficient scalar instructions in order to generate efficient vector instructions, adding new instructions for datatransfer/conversion between FPRs and GPRs multiplies the savings.
In addition, the vast majority of GPR <> FPR datatransfers are as part of a FP <> Integer conversion sequence, therefore reducing the number of instructions required is a priority.
Therefore, we are proposing adding:
 FPR loadimmediate instructions, one equivalent to
BF16
, the other increasing accuracy toFP32
 FPR <> GPR datatransfer instructions that just copy bits without conversion
 FPR <> GPR combined datatransfer/conversion instructions that do Integer <> FP conversions
If adding new Integer <> FP conversion instructions, the opportunity may be taken to modernise the instructions and make them wellsuited for common/important conversion sequences:
 Int > Float
 standard IEEE754  used by most languages and CPUs
 Float > Int
 standard OpenPOWER  saturation with NaN converted to minimum valid integer
 Java/Saturating  saturation with NaN converted to 0
 JavaScript  modulo wrapping with Inf/NaN converted to 0
The assembly listings in the appendix show how costly some of these languagespecific conversions are: JavaScript, the worst case, is 32 scalar instructions including seven branch instructions.
Proposed New Scalar Instructions
All of the following instructions use the standard OpenPower conversion to/from 64bit float format when reading/writing a 32bit float from/to a FPR. All integers however are sourced/stored in the GPR.
Integer operands and results being in the GPR is the key differentiator between the proposed instructions (the entire rationale) compared to existing Scalar Power ISA. In all existing Power ISA Scalar conversion instructions, all operands are FPRs, even if the format of the source or destination data is actually a scalar integer.
(The existing Scalar instructions being FPFP only is based on an assumption that VSX will be implemented, and VSX is not part of the SFFS Compliancy Level. An earlier version of the Power ISA used to have similar FPR<>GPR instructions to these: they were deprecated due to this incorrect assumption that VSX would always be present).
Note that source and destination widths can be overridden by SimpleV SVP64, and that SVP64 also has Saturation Modes in addition to those independently described here. SVP64 Overrides and Saturation work on both Fixed and Floating Point operands and results. The interactions with SVP64 are explained in the appendix
Float load immediate
These are like a variant of mtfpr
and oris
, combined.
Power ISA currently requires a large
number of instructions to get Floating Point constants into registers.
fmvis
on its own is equivalent to BF16 to FP32/64 conversion,
but if followed up by fishmv
an additional 16 bits of accuracy in the
mantissa may be achieved.
These instructions always save
resources compared to FPload for exactly the same reason
that li
saves resources: an L1DataCache and memory read
is avoided.
IBM may consider it worthwhile to extend these two instructions to
v3.1 Prefixed (pfmvis
and pfishmv
: 8RR, imm0 extended).
If so it is recommended that
pfmvis
load a full FP32 immediate and pfishmv
supplies the three high
missing exponent bits (numbered 8 to 10) and the lower additional
29 mantissa bits (23 to 51) needed to construct a full FP64 immediate.
Strictly speaking the sequence fmvis fishmv pfishmv
achieves the
same effect in the same number of bytes as pfmvis pfishmv
,
making pfmvis
redundant.
Just as Floatingpoint Load does not set FP Flags neither does fmvis or fishmv. As fishmv is specifically intended to work in conjunction with fmvis to provide additional accuracy, all bits other than those which would have been set by a prior fmvis instruction are deliberately ignored. (If these instructions involved reading from registers rather than immediates it would be a different story).
Load BF16 Immediate
fmvis FRS, D
Reinterprets D << 16
as a 32bit float, which is then converted to a
64bit float and written to FRS
. This is equivalent to reinterpreting
D
as a BF16
and converting to 64bit float.
There is no need for an Rc=1 variant because this is an immediate loading
instruction.
Example:
# clearing a FPR
fmvis f4, 0 # writes +0.0 to f4
# loading handy constants
fmvis f4, 0x8000 # writes 0.0 to f4
fmvis f4, 0x3F80 # writes +1.0 to f4
fmvis f4, 0xBF80 # writes 1.0 to f4
fmvis f4, 0xBFC0 # writes 1.5 to f4
fmvis f4, 0x7FC0 # writes +qNaN to f4
fmvis f4, 0x7F80 # writes +Infinity to f4
fmvis f4, 0xFF80 # writes Infinity to f4
fmvis f4, 0x3FFF # writes +1.9921875 to f4
# clearing 128 FPRs with 2 SVP64 instructions
# by issuing 32 vec4 (subvector length 4) ops
setvli VL=MVL=32
sv.fmvis/vec4 f0, 0 # writes +0.0 to f0f127
Important: If the float load immediate instruction(s) are left out,
change all GPR to FPR conversion instructions
to instead write +0.0
if RA
is register 0
, at least
allowing clearing FPRs.
fmvis
fits with DXForm:
05  610  1115  1625  2630  31  Form 

Major  FRS  d1  d0  XO  d2  DXForm 
Pseudocode:
bf16 = d0  d1  d2 # create BF16 immediate
fp32 = bf16  [0]*16 # convert BF16 to FP32
FRS = DOUBLE(fp32) # convert FP32 to FP64
Special registers altered:
None
Float Immediate SecondHalf MV
fishmv FRS, D
DXForm:
05  610  1115  1625  2630  31  Form 

Major  FRS  d1  d0  XO  d2  DXForm 
Strategically similar to how oris
is used to construct
32bit Integers, an additional 16bits of immediate is
inserted into FRS
to extend its accuracy to
a full FP32 (stored as usual in FP64 Format within the FPR).
If a prior fmvis
instruction had been used to
set the upper 16bits of an FP32 value, fishmv
contains the
lower 16bits.
The key difference between using li
and oris
to construct 32bit
GPR Immediates and fishmv
is that the fmvis
will have converted
the BF16
immediate to FP64 (Double) format.
This is taken into consideration
as can be seen in the pseudocode below.
Pseudocode:
fp32 < SINGLE((FRS)) # convert to FP32
fp32[16:31] < d0  d1  d2 # replace LSB half
FRS < DOUBLE(fp32) # convert back to FP64
Special registers altered:
None
This instruction performs a ReadModifyWrite. FRS is read, the additional 16 bit immediate inserted, and the result also written to FRS
Example:
# these two combined instructions write 0x3f808000
# into f4 as an FP32 to be converted to an FP64.
# actual contents in f4 after conversion: 0x3ff0_1000_0000_0000
# first the upper bits, happens to be +1.0
fmvis f4, 0x3F80 # writes +1.0 to f4
# now write the lower 16 bits of an FP32
fishmv f4, 0x8000 # writes +1.00390625 to f4
Floatingpoint to Integer Conversion Overview
IEEE 754 does not specify what results are obtained when converting a NaN
or outofrange floatingpoint value to integer, so different programming
languages and ISAs have made different choices. The different conversion
modes supported by the cffpr
instruction are as follows:
PType:
Used by most other PowerISA instructions, as well as commonly used floatingpoint to integer conversions on x86.SType:
Used for several notable programming languages: Java's conversion from
float
/double
tolong
/int
^{1}  Rust's
as
operator^{2}  LLVM's
llvm.fptosi.sat
^{3} andllvm.fptoui.sat
^{4} intrinsics  SPIRV's OpenCL dialect's
OpConvertFToU
^{5} andOpConvertFToS
^{6} instructions when decorated with theSaturatedConversion
^{7} decorator.  Also WebAssembly's
trunc_sat_u
^{8} andtrunc_sat_s
^{9} instructions,
 Java's conversion from
EType:
Used for ECMAScript'sToInt32
abstract operation^{10}. Also implemented in ARMv8.3A as theFJCVTZS
instruction^{11}.
Floatingpoint to Integer Conversion Semantics Summary
Let round
be the result of bfp_ROUND_TO_INTEGER(rmode, input)
.
Let w
be the number of bits in the result's type.
The result of Floatingpoint to Integer conversion is as follows:
++++
Type Result  Category of rounding 
  Sign +++++++
   NaN  +Inf  Inf  > Max  < Min  Else 
      Possible  Possible 
      Result  Result  
+++++++++
 P Unsigned 0  2^w  1  0  2^w  1  0  round 
 ++++++++
  Signed  2^(w1)  2^(w1)1  2^(w1)  2^(w1)1  2^(w1) round 
+++++++++
 S Unsigned 0  2^w  1  0  2^w  1  0  round 
 ++++++++
  Signed  0  2^(w1)1  2^(w1)  2^(w1)1  2^(w1) round 
+++++++++
 E  Either  0  round & (2^w  1) 
+++++
Immediate Tables
Tables that are used by
mffpr[s][.]
/mtfpr[s]
/cffpr[o][.]
/ctfpr[s][.]
:
IT
 Integer Type
IT 
Integer Type  Assembly Alias Mnemonic 

0  Signed 32bit  <op>w 
1  Unsigned 32bit  <op>uw 
2  Signed 64bit  <op>d 
3  Unsigned 64bit  <op>ud 
CVM
 Float to Integer Conversion Mode
CVM 
rounding_mode 
Semantics 

000  from FPSCR 
PType 
001  Truncate  PType 
010  from FPSCR 
SType 
011  Truncate  SType 
100  from FPSCR 
EType 
101  Truncate  EType 
rest    invalid 
\newpage{}
Move To/From FloatingPoint Register Instructions
These instructions perform a copy from one register file to another, as if by using a GPR/FPR store, followed by a FPR/GPR load.
Move From FloatingPoint Register
mffpr RT, FRB
mffpr. RT, FRB
05  610  1115  1620  2130  31  Form 

PO  RT  //  FRB  XO  Rc  XForm 
RT < (FRB)
The contents of FPR[FRB]
are placed into GPR[RT]
.
Special Registers altered:
CR0 (if Rc=1)
Architecture Note:
mffpr
is equivalent to the combination of stfd
followed by ld
.
Architecture Note:
mffpr
is a separate instruction from mfvsrd
because mfvsrd
requires
VSX which may not be available on simpler implementations.
Additionally, SVP64 may treat VSX instructions differently than SFFS
instructions in a future version of the architecture.
Move From FloatingPoint Register Single
mffprs RT, FRB
mffprs. RT, FRB
05  610  1115  1620  2130  31  Form 

PO  RT  //  FRB  XO  Rc  XForm 
RT < [0] * 32  SINGLE((FRB))
The contents of FPR[FRB]
are converted to BFP32 by using SINGLE
, then
zeroextended to 64bits, and the result stored in GPR[RT]
.
Special Registers altered:
CR0 (if Rc=1)
Architecture Note:
mffprs
is equivalent to the combination of stfs
followed by lwz
.
\newpage{}
Move To FloatingPoint Register
mtfpr FRT, RB
05  610  1115  1620  2130  31  Form 

PO  FRT  //  RB  XO  //  XForm 
FRT < (RB)
The contents of GPR[RB]
are placed into FPR[FRT]
.
Special Registers altered:
None
Architecture Note:
mtfpr
is equivalent to the combination of std
followed by lfd
.
Architecture Note:
mtfpr
is a separate instruction from mtvsrd
because mtvsrd
requires
VSX which may not be available on simpler implementations.
Additionally, SVP64 may treat VSX instructions differently than SFFS
instructions in a future version of the architecture.
Move To FloatingPoint Register Single
mtfprs FRT, RB
05  610  1115  1620  2130  31  Form 

PO  FRT  //  RB  XO  //  XForm 
FRT < DOUBLE((RB)[32:63])
The contents of bits 32:63 of GPR[RB]
are converted to BFP64 by using
DOUBLE
, then the result is stored in GPR[RT]
.
Special Registers altered:
None
Architecture Note:
mtfprs
is equivalent to the combination of stw
followed by lfs
.
\newpage{}
Conversion To/From FloatingPoint Register Instructions
Convert To FloatingPoint Register
ctfpr FRT, RB, IT
ctfpr. FRT, RB, IT
05  610  1112  1315  1620  2130  31  Form 

PO  FRT  IT  //  RB  XO  Rc  XForm 
if IT[0] = 0 then # 32bit int > 64bit float
# rounding never necessary, so don't touch FPSCR
# based off xvcvsxwdp
if IT = 0 then # Signed 32bit
src < bfp_CONVERT_FROM_SI32((RB)[32:63])
else # IT = 1  Unsigned 32bit
src < bfp_CONVERT_FROM_UI32((RB)[32:63])
FRT < bfp64_CONVERT_FROM_BFP(src)
else
# rounding may be necessary. based off xscvuxdsp
reset_xflags()
switch(IT)
case(0): # Signed 32bit
src < bfp_CONVERT_FROM_SI32((RB)[32:63])
case(1): # Unsigned 32bit
src < bfp_CONVERT_FROM_UI32((RB)[32:63])
case(2): # Signed 64bit
src < bfp_CONVERT_FROM_SI64((RB))
default: # Unsigned 64bit
src < bfp_CONVERT_FROM_UI64((RB))
rnd < bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, src)
result < bfp64_CONVERT_FROM_BFP(rnd)
cls < fprf_CLASS_BFP64(result)
if xx_flag = 1 then SetFX(FPSCR.XX)
FRT < result
FPSCR.FPRF < cls
FPSCR.FR < inc_flag
FPSCR.FI < xx_flag
Convert from a unsigned/signed 32/64bit integer in RB to a 64bit float in FRT.
If converting from a unsigned/signed 32bit integer to a 64bit float,
rounding is never necessary, so FPSCR
is unmodified and exceptions are
never raised. Otherwise, FPSCR
is modified and exceptions are raised
as usual.
Rc=1 tests FRT and sets CR1, exactly like all other Scalar FloatingPoint operations.
Special Registers altered:
CR1 (if Rc=1)
FPRF FR FI FX XX (if IT[0]=1)
Assembly Aliases
Assembly Alias  Full Instruction 

ctfprw FRT, RB 
ctfpr FRT, RB, 0 
ctfprw. FRT, RB 
ctfpr. FRT, RB, 0 
ctfpruw FRT, RB 
ctfpr FRT, RB, 1 
ctfpruw. FRT, RB 
ctfpr. FRT, RB, 1 
ctfprd FRT, RB 
ctfpr FRT, RB, 2 
ctfprd. FRT, RB 
ctfpr. FRT, RB, 2 
ctfprud FRT, RB 
ctfpr FRT, RB, 3 
ctfprud. FRT, RB 
ctfpr. FRT, RB, 3 
\newpage{}
Convert To FloatingPoint Register Single
ctfprs FRT, RB, IT
ctfprs. FRT, RB, IT
05  610  1112  1315  1620  2130  31  Form 

PO  FRT  IT  //  RB  XO  Rc  XForm 
# rounding may be necessary. based off xscvuxdsp
reset_xflags()
switch(IT)
case(0): # Signed 32bit
src < bfp_CONVERT_FROM_SI32((RB)[32:63])
case(1): # Unsigned 32bit
src < bfp_CONVERT_FROM_UI32((RB)[32:63])
case(2): # Signed 64bit
src < bfp_CONVERT_FROM_SI64((RB))
default: # Unsigned 64bit
src < bfp_CONVERT_FROM_UI64((RB))
rnd < bfp_ROUND_TO_BFP32(FPSCR.RN, src)
result32 < bfp32_CONVERT_FROM_BFP(rnd)
cls < fprf_CLASS_BFP32(result32)
result < DOUBLE(result32)
if xx_flag = 1 then SetFX(FPSCR.XX)
FRT < result
FPSCR.FPRF < cls
FPSCR.FR < inc_flag
FPSCR.FI < xx_flag
Convert from a unsigned/signed 32/64bit integer in RB to a 32bit
float in FRT, following the usual 32bit float in 64bit float format.
FPSCR
is modified and exceptions are raised as usual.
Rc=1 tests FRT and sets CR1, exactly like all other Scalar FloatingPoint operations.
Special Registers altered:
CR1 (if Rc=1)
FPRF FR FI FX XX
Assembly Aliases
Assembly Alias  Full Instruction 

ctfprws FRT, RB 
ctfpr FRT, RB, 0 
ctfprws. FRT, RB 
ctfpr. FRT, RB, 0 
ctfpruws FRT, RB 
ctfpr FRT, RB, 1 
ctfpruws. FRT, RB 
ctfpr. FRT, RB, 1 
ctfprds FRT, RB 
ctfpr FRT, RB, 2 
ctfprds. FRT, RB 
ctfpr. FRT, RB, 2 
ctfpruds FRT, RB 
ctfpr FRT, RB, 3 
ctfpruds. FRT, RB 
ctfpr. FRT, RB, 3 
\newpage{}
Convert From FloatingPoint Register
cffpr RT, FRB, CVM, IT
cffpr. RT, FRB, CVM, IT
cffpro RT, FRB, CVM, IT
cffpro. RT, FRB, CVM, IT
05  610  1112  1315  1620  21  2230  31  Form 

PO  RT  IT  CVM  FRB  OE  XO  Rc  XOForm 
# based on xscvdpuxws
reset_xflags()
src < bfp_CONVERT_FROM_BFP64((FRB))
switch(IT)
case(0): # Signed 32bit
range_min < bfp_CONVERT_FROM_SI32(0x8000_0000)
range_max < bfp_CONVERT_FROM_SI32(0x7FFF_FFFF)
js_mask < 0x0000_0000_FFFF_FFFF
case(1): # Unsigned 32bit
range_min < bfp_CONVERT_FROM_UI32(0)
range_max < bfp_CONVERT_FROM_UI32(0xFFFF_FFFF)
js_mask < 0x0000_0000_FFFF_FFFF
case(2): # Signed 64bit
range_min < bfp_CONVERT_FROM_SI64(0x8000_0000_0000_0000)
range_max < bfp_CONVERT_FROM_SI64(0x7FFF_FFFF_FFFF_FFFF)
js_mask < 0xFFFF_FFFF_FFFF_FFFF
default: # Unsigned 64bit
range_min < bfp_CONVERT_FROM_UI64(0)
range_max < bfp_CONVERT_FROM_UI64(0xFFFF_FFFF_FFFF_FFFF)
js_mask < 0xFFFF_FFFF_FFFF_FFFF
if (CVM[2] = 1)  (FPSCR.RN = 0b01) then
rnd < bfp_ROUND_TO_INTEGER_TRUNC(src)
else if FPSCR.RN = 0b00 then
rnd < bfp_ROUND_TO_INTEGER_NEAR_EVEN(src)
else if FPSCR.RN = 0b10 then
rnd < bfp_ROUND_TO_INTEGER_CEIL(src)
else if FPSCR.RN = 0b11 then
rnd < bfp_ROUND_TO_INTEGER_FLOOR(src)
switch(CVM)
case(0, 1): # PType
if IsNaN(rnd) then
result < si64_CONVERT_FROM_BFP(range_min)
else if bfp_COMPARE_GT(rnd, range_max) then
result < ui64_CONVERT_FROM_BFP(range_max)
else if bfp_COMPARE_LT(rnd, range_min) then
result < si64_CONVERT_FROM_BFP(range_min)
else if IT[1] = 1 then # Unsigned 32/64bit
result < ui64_CONVERT_FROM_BFP(rnd)
else # Signed 32/64bit
result < si64_CONVERT_FROM_BFP(rnd)
case(2, 3): # SType
if IsNaN(rnd) then
result < [0] * 64
else if bfp_COMPARE_GT(rnd, range_max) then
result < ui64_CONVERT_FROM_BFP(range_max)
else if bfp_COMPARE_LT(rnd, range_min) then
result < si64_CONVERT_FROM_BFP(range_min)
else if IT[1] = 1 then # Unsigned 32/64bit
result < ui64_CONVERT_FROM_BFP(rnd)
else # Signed 32/64bit
result < si64_CONVERT_FROM_BFP(rnd)
default: # EType
# CVM = 6, 7 are illegal instructions
# using a 128bit intermediate works here because the largest type
# this instruction can convert from has 53 significand bits, and
# the largest type this instruction can convert to has 64 bits,
# and the sum of those is strictly less than the 128 bits of the
# intermediate result.
limit < bfp_CONVERT_FROM_UI128([1] * 128)
if IsInf(rnd)  IsNaN(rnd) then
result < [0] * 64
else if bfp_COMPARE_GT(bfp_ABSOLUTE(rnd), limit) then
result < [0] * 64
else
result128 < si128_CONVERT_FROM_BFP(rnd)
result < result128[64:127] & js_mask
switch(IT)
case(0): # Signed 32bit
result < EXTS64(result[32:63])
result_bfp < bfp_CONVERT_FROM_SI32(result[32:63])
case(1): # Unsigned 32bit
result < EXTZ64(result[32:63])
result_bfp < bfp_CONVERT_FROM_UI32(result[32:63])
case(2): # Signed 64bit
result_bfp < bfp_CONVERT_FROM_SI64(result)
default: # Unsigned 64bit
result_bfp < bfp_CONVERT_FROM_UI64(result)
overflow < 0 # signals SO only when OE = 1
if IsNaN(src)  ¬bfp_COMPARE_EQ(rnd, result_bfp) then
overflow < 1 # signals SO only when OE = 1
vxcvi_flag < 1
xx_flag < 0
inc_flag < 0
else
xx_flag < ¬bfp_COMPARE_EQ(src, result_bfp)
inc_flag < bfp_COMPARE_GT(bfp_ABSOLUTE(result_bfp), bfp_ABSOLUTE(src))
if vxsnan_flag = 1 then SetFX(FPSCR.VXSNAN)
if vxcvi_flag = 1 then SetFX(FPSCR.VXCVI)
if xx_flag = 1 then SetFX(FPSCR.XX)
vx_flag < vxsnan_flag  vxcvi_flag
vex_flag < FPSCR.VE & vx_flag
if vex_flag = 0 then
RT < result
FPSCR.FPRF < undefined
FPSCR.FR < inc_flag
FPSCR.FI < xx_flag
else
FPSCR.FR < 0
FPSCR.FI < 0
Convert from 64bit float in FRB to a unsigned/signed 32/64bit integer
in RT, with the conversion overflow/rounding semantics following the
chosen CVM
value. FPSCR
is modified and exceptions are raised as usual.
This instruction has an Rc=1 mode which sets CR0 in the normal
way for any instructions producing a GPR result. Additionally, when OE=1,
if the numerical value of the FP number is not 100% accurately preserved
(due to truncation or saturation and including when the FP number was
NaN) then this is considered to be an Integer Overflow condition, and
CR0.SO, XER.SO and XER.OV are all set as normal for any GPR instructions
that overflow. When RT
is not written (vex_flag = 1
), all CR0 bits
except SO are undefined.
Special Registers altered:
CR0 (if Rc=1)
XER SO, OV, OV32 (if OE=1)
FPRF=0bUUUUU FR FI FX XX VXSNAN VXCV
Assembly Aliases
Assembly Alias  Full Instruction 

cffprw RT, FRB, CVM 
cffpr RT, FRB, CVM, 0 
cffprw. RT, FRB, CVM 
cffpr. RT, FRB, CVM, 0 
cffprwo RT, FRB, CVM 
cffpro RT, FRB, CVM, 0 
cffprwo. RT, FRB, CVM 
cffpro. RT, FRB, CVM, 0 
cffpruw RT, FRB, CVM 
cffpr RT, FRB, CVM, 1 
cffpruw. RT, FRB, CVM 
cffpr. RT, FRB, CVM, 1 
cffpruwo RT, FRB, CVM 
cffpro RT, FRB, CVM, 1 
cffpruwo. RT, FRB, CVM 
cffpro. RT, FRB, CVM, 1 
cffprd RT, FRB, CVM 
cffpr RT, FRB, CVM, 2 
cffprd. RT, FRB, CVM 
cffpr. RT, FRB, CVM, 2 
cffprdo RT, FRB, CVM 
cffpro RT, FRB, CVM, 2 
cffprdo. RT, FRB, CVM 
cffpro. RT, FRB, CVM, 2 
cffprud RT, FRB, CVM 
cffpr RT, FRB, CVM, 3 
cffprud. RT, FRB, CVM 
cffpr. RT, FRB, CVM, 3 
cffprudo RT, FRB, CVM 
cffpro RT, FRB, CVM, 3 
cffprudo. RT, FRB, CVM 
cffpro. RT, FRB, CVM, 3 

Java
float
/double
tolong
/int
conversion: https://docs.oracle.com/javase/specs/jls/se16/html/jls5.html#jls5.1.3↩ 
Rust's
as
operator: https://doc.rustlang.org/1.70.0/reference/expressions/operatorexpr.html#numericcast↩ 
LLVM's
llvm.fptosi.sat
intrinsic: https://llvm.org/docs/LangRef.html#llvmfptosisatintrinsic↩ 
LLVM's
llvm.fptoui.sat
intrinsic: https://llvm.org/docs/LangRef.html#llvmfptouisatintrinsic↩ 
SPIRV's
OpConvertFToU
instruction: https://www.khronos.org/registry/spirv/specs/unified1/SPIRV.html#OpConvertFToU↩ 
SPIRV's
OpConvertFToS
instruction: https://www.khronos.org/registry/spirv/specs/unified1/SPIRV.html#OpConvertFToS↩ 
SPIRV's
SaturatedConversion
decorator:
https://www.khronos.org/registry/spirv/specs/unified1/SPIRV.html#_a_id_decoration_a_decoration↩ 
WASM's
trunc_sat_u
: https://webassembly.github.io/spec/core/exec/numerics.html#optruncsatu↩ 
WASM's
trunc_sat_s
: https://webassembly.github.io/spec/core/exec/numerics.html#optruncsats↩ 
ECMAScript's
ToInt32
abstract operation: https://262.ecmainternational.org/14.0/#sectoint32↩ 
ARM's
FJCVTZS
instruction: https://developer.arm.com/documentation/dui0801/g/hko1477562192868↩