Resources and Specifications

This page aims to collect all the resources and specifications we need in one place for quick access. We will try our best to keep links here up-to-date. Feel free to add more links here.

Getting Started

This section is primarily a series of useful links found online

Is Open Source Hardware Profitable?

RaptorCS on FOSS Hardware Interview


Overview of the user ISA:

Raymond Chen's PowerPC series

OpenPOWER OpenFSI Spec (2016)



RISC-V Instruction Set Architecture

PLEASE UPDATE - we are no longer implementing full RISCV, only user-space RISCV

The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name of the project implies, we will be following the RISC-V ISA I due to it being open-source and also because of the huge software and hardware ecosystem building around it. There are other open-source ISAs but none of them have the same momentum and energy behind it as RISC-V.

To fully take advantage of the RISC-V ecosystem, it is important to be compliant with the RISC-V standards. Doing so will allow us to to reuse most software as-is and avoid major forks.

Note: As far as I know, we aren't using the RISC-V V Extension directly at the moment (correction: we were never going to). However, there are many wiki pages that make a reference to the V extension so it would be good to include it here as a reference for comparative/informative purposes with regard to Simple-V.

Radix MMU


D-Cache Possible Optimizations papers and links

BW Enhancing Shared L1 Cache Design research done in cooperation with AMD

RTL Arithmetic SQRT, FPU etc.

Wallace vs Dadda Multipliers


CORDIC and related algorithms

IEEE Standard for Floating-Point Arithmetic (IEEE 754)

Almost all modern computers follow the IEEE Floating-Point Standard. Of course, we will follow it as well for interoperability.

Note: Even though this is such an important standard used by everyone, it is unfortunately not freely available and requires a payment to access. However, each of the Libre RISC-V members already have access to the document.

Among other things, has a nice explanation on arithmetic, rounding modes and the sticky bit.

Nice resource on rounding errors (ulps and epsilon) and the "table maker's dilemma".

Past FPU Mistakes to learn from

The Khronos Group creates open standards for authoring and acceleration of graphics, media, and computation. It is a requirement for our hybrid CPU/GPU to be compliant with these standards as well as with IEEE754, in order to be commercially-competitive in both areas: especially Vulkan and OpenCL being the most important. SPIR-V is also important for the Kazan driver.

Thus the zfpacc proposal has been created which permits runtime dynamic switching between different accuracy levels, in userspace applications.

SPIR-V Main Page Link

Vulkan Main Page Link

OpenCL Main Page

Note: We are implementing hardware accelerated Vulkan and OpenCL while relying on other software projects to translate APIs to Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software.

Graphics and Compute API Stack

I found this informative post that mentions Kazan and a whole bunch of other stuff. It looks like many APIs can be emulated on top of Vulkan, although performance is not evaluated.

3D Graphics Texture compression software and hardware

Various POWER Communities

  • An effort to make a 100% Libre POWER Laptop The T2080 is a POWER8 chip.
  • Power Progress Community Supporting/Raising awareness of various POWER related open projects on the FOSS community
  • OpenPOWER Promotes and ensure compliance with the Power ISA amongst members.
  • OpenCapi High performance interconnect for POWER machines. One of the big advantages of the POWER architecture. Notably more performant than PCIE Gen4, and is designed to be layered on top of the physical PCIE link.
  • OpenPOWER “Virtual Coffee” Calls Truly open bi-weekly teleconference lines for anybody interested in helping advance or adopting the POWER architecture.


Free Silicon Conference

The conference brought together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference covered the full spectrum of the design process, from system architecture, to layout and verification.

Note: The rest of LIP6's website is in French, but there is a UK flag in the corner that gives the English version.

The OpenROAD Project

OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source layout generation flow (RTL-to-GDS).

Other RISC-V GPU attempts

TODO: Get in touch and discuss collaboration

Tests, Benchmarks, Conformance, Compliance, Verification, etc.

RISC-V Tests

RISC-V Foundation is in the process of creating an official conformance test. It's still in development as far as I can tell.


IEEE 754 Testing/Emulation

IEEE 754 has no official tests for floating-point but there are well-known third party tools to check such as John Hauser's TestFloat.

There is also his SoftFloat library, which is a software emulation library for IEEE 754.

Jacob is also working on an IEEE 754 software emulation library written in Rust which also has Python bindings:

A cool paper I came across in my research is "IeeeCC754++ : An Advanced Set of Tools to Check IEEE 754-2008 Conformity" by Dr. Matthias Hüsken.

Khronos Tests

OpenCL Conformance Tests

Vulkan Conformance Tests

MAJOR NOTE: We are not allowed to say we are compliant with any of the Khronos standards until we actually make an official submission, do the paperwork, and pay the relevant fees.

Formal Verification

Formal verification of Libre RISC-V ensures that it is bug-free in regards to what we specify. Of course, it is important to do the formal verification as a final step in the development process before we produce thousands or millions of silicon.

Some learning resources I found in the community:



Adding new instructions:

Branch Prediction

Python RTL Tools


ASIC tape-out pricing


Good Programming/Design Practices

12 skills summary

Analog Simulation

Libre-SOC Standards

This list auto-generated from a page tag "standards":

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av opcodes
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cr int predication
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vector swizzle
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16 bit compressed
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masked vector chaining
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vector ops
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abridged spec
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vblock format
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sv prefix proposal
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Server setup


Really Useful Stuff

Digilent Arty


CircuitJS experiments

ASIC Timing and Design flow resources

Geometric Haskell Library