Resources and Specifications

This page aims to collect all the resources and specifications we need in one place for quick access. We will try our best to keep links here up-to-date. Feel free to add more links here.

Getting Started

This section is primarily a series of useful links found online

Is Open Source Hardware Profitable?

RaptorCS on FOSS Hardware Interview


Overview of the user ISA:

OpenPOWER OpenFSI Spec (2016)

Energy-efficient cores


Open Access Publication locations


ppc64 ELF ABI

Similar concepts

Other GPU Specifications

  • MALI Midgard
  • Nyuzi
  • VideoCore IV
  • etnaviv

Other CPUs and ISAs worth considering

  • Mitch Alsup 66000
  • Hitachi Sh2
  • 68080 except Length-Decode is a pig for Multi-Issue

Package Management


Radix MMU


D-Cache Possible Optimizations papers and links

BW Enhancing Shared L1 Cache Design research done in cooperation with AMD

RTL Arithmetic SQRT, FPU etc.

Wallace vs Dadda Multipliers


CORDIC and related algorithms

IEEE Standard for Floating-Point Arithmetic (IEEE 754)

Almost all modern computers follow the IEEE Floating-Point Standard. Of course, we will follow it as well for interoperability.

Note: Even though this is such an important standard used by everyone, it is unfortunately not freely available and requires a payment to access. However, each of the Libre-SOC members already have access to the document.

Among other things, has a nice explanation on arithmetic, rounding modes and the sticky bit.

Nice resource on rounding errors (ulps and epsilon) and the "table maker's dilemma".

Past FPU Mistakes to learn from

Khronos Standards

The Khronos Group creates open standards for authoring and acceleration of graphics, media, and computation. It is a requirement for our hybrid CPU/GPU to be compliant with these standards as well as with IEEE754, in order to be commercially-competitive in both areas: especially Vulkan and OpenCL being the most important. SPIR-V is also important for the Kazan driver.

Thus the zfpacc proposal has been created which permits runtime dynamic switching between different accuracy levels, in userspace applications.

SPIR-V Main Page Link

Vulkan Main Page Link

OpenCL Main Page

Note: We are implementing hardware accelerated Vulkan and OpenCL while relying on other software projects to translate APIs to Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software.

Open Source (CC BY + MIT) DirectX specs (by Microsoft, but not official specs)

Graphics and Compute API Stack

I found this informative post that mentions Kazan and a whole bunch of other stuff. It looks like many APIs can be emulated on top of Vulkan, although performance is not evaluated.

3D Graphics Texture compression software and hardware

Various POWER Communities

  • An effort to make a 100% Libre POWER Laptop The T2080 is a POWER8 chip.
  • Power Progress Community Supporting/Raising awareness of various POWER related open projects on the FOSS community
  • OpenPOWER Promotes and ensure compliance with the Power ISA amongst members.
  • OpenCapi High performance interconnect for POWER machines. One of the big advantages of the POWER architecture. Notably more performant than PCIE Gen4, and is designed to be layered on top of the physical PCIE link.
  • OpenPOWER “Virtual Coffee” Calls Truly open bi-weekly teleconference lines for anybody interested in helping advance or adopting the POWER architecture.


see conferences


Note: The rest of LIP6's website is in French, but there is a UK flag in the corner that gives the English version.

Logical Equivalence and extraction

  • CVC


image to GDS-II


The OpenROAD Project

OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source layout generation flow (RTL-to-GDS).

Other RISC-V GPU attempts

TODO: Get in touch and discuss collaboration

Tests, Benchmarks, Conformance, Compliance, Verification, etc.

RISC-V Tests

RISC-V Foundation is in the process of creating an official conformance test. It's still in development as far as I can tell.


IEEE 754 Testing/Emulation

IEEE 754 has no official tests for floating-point but there are well-known third party tools to check such as John Hauser's TestFloat.

There is also his SoftFloat library, which is a software emulation library for IEEE 754.

Jacob is also working on an IEEE 754 software emulation library written in Rust which also has Python bindings:

A cool paper I came across in my research is "IeeeCC754++ : An Advanced Set of Tools to Check IEEE 754-2008 Conformity" by Dr. Matthias Hüsken.

Khronos Tests

OpenCL Conformance Tests

Vulkan Conformance Tests

MAJOR NOTE: We are not allowed to say we are compliant with any of the Khronos standards until we actually make an official submission, do the paperwork, and pay the relevant fees.

Formal Verification

Formal verification of Libre RISC-V ensures that it is bug-free in regards to what we specify. Of course, it is important to do the formal verification as a final step in the development process before we produce thousands or millions of silicon.

Some learning resources I found in the community:



Bus Architectures

Vector Processors


Adding new instructions:

Branch Prediction

Python RTL Tools


Real/Physical Projects

ASIC tape-out pricing


Good Programming/Design Practices

12 skills summary

Analog Simulation

Libre-SOC Standards

This list auto-generated from a page tag "standards":

tern bin
Posted Wed Apr 26 14:52:58 2023
Posted Thu Apr 20 16:34:32 2023
po9 encoding
Posted Mon Apr 3 11:49:21 2023
Posted Fri Jul 15 19:27:17 2022
Posted Mon Jun 20 17:34:26 2022
Posted Sat Jun 18 12:18:27 2022
vector isa comparison
Posted Fri Jun 17 11:35:41 2022
3d vector ops
Posted Thu Jun 16 12:18:39 2022
compliancy levels
Posted Tue Jun 7 11:58:44 2022
Posted Thu Apr 21 09:20:46 2022
Posted Tue Apr 19 13:49:00 2022
Posted Wed Sep 15 17:41:26 2021
cr ops
Posted Sun Aug 29 19:35:33 2021
Posted Wed Aug 4 13:29:22 2021
Posted Sun Aug 1 19:21:58 2021
register type tags
Posted Wed Jun 30 20:54:14 2021
Posted Thu Jun 3 22:25:34 2021
int fp mv
Posted Sat May 29 09:34:48 2021
16 bit compressed
Posted Mon May 10 21:37:20 2021
Posted Mon May 10 21:37:20 2021
av opcodes
Posted Mon May 10 21:37:20 2021
Posted Mon May 10 21:37:20 2021
Posted Mon May 10 21:37:20 2021
cr int predication
Posted Mon May 10 21:37:20 2021
Posted Mon May 10 21:37:20 2021
Posted Mon May 10 21:37:20 2021
Posted Mon May 10 21:37:20 2021
Posted Mon May 10 21:37:20 2021
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Posted Mon May 10 21:37:20 2021
Posted Mon May 10 21:37:20 2021
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Posted Mon May 10 21:37:20 2021
Posted Mon May 10 21:37:20 2021
vector ops
Posted Mon May 10 21:37:20 2021
Posted Tue Jun 25 14:21:45 2019

Server setup


Really Useful Stuff

Digilent Arty


CircuitJS experiments

Logic Simulator 2


  1. Micro-subset verilog-like DSL for coding the array of logic gates (parsed using Antlr)
  2. Monaco-based code editor with automatic linting/error reporting, smart indentation, code folding, hints
  3. IDE docking ui courtesy of JupyterLab's Lumino widgets
  4. Schematic visualisation courtesy of d3-hwschematic
  5. Testbench simulation with graphical trace output and schematic animation
  6. Circuit description as gates, boolean logic or verilog behavioural model
  7. Generate arbitrary outputs from truth table and Sum of Products or Karnaugh Map

[from the GitHub page. As of 2021/03/29]

ASIC Timing and Design flow resources

Geometric Haskell Library

Handy Compiler Algorithms for SimpleV

Requires aligned registers:

More general:

TODO investigate
     The RAD750 system has a price that is comparable to the RAD6000, the latter of which as of 2002 was listed at US$200,000 (equivalent to $284,292 in 2019).
     You might also want to check out
     “TCL has served us well, over the years, allowing us to provide an API, and at the same time ensure nobody will ever use it. I will miss it”.
     FuseSoC is used by MicroWatt and Western Digital cores
     OpenTitan also uses FuseSoC
     LowRISC is UK based - mirror neural atrophy results in destruction of empathy