Resources and Specifications
This page aims to collect all the resources and specifications we need in one place for quick access. We will try our best to keep links here up-to-date. Feel free to add more links here.
- Resources and Specifications
- Getting Started
- OpenPOWER ISA
- JTAG
- RISC-V Instruction Set Architecture
- Radix MMU
- D-Cache
- BW Enhancing Shared L1 Cache Design research done in cooperation with AMD
- RTL Arithmetic SQRT, FPU etc.
- Khronos Standards
- Graphics and Compute API Stack
- 3D Graphics Texture compression software and hardware
- Various POWER Communities
- Conferences
- The OpenROAD Project
- Other RISC-V GPU attempts
- Tests, Benchmarks, Conformance, Compliance, Verification, etc.
- LLVM
- Branch Prediction
- Python RTL Tools
- Other
- Real/Physical Projects
- ASIC tape-out pricing
- Funding
- Good Programming/Design Practices
- 12 skills summary
- Analog Simulation
- Libre-SOC Standards
- Server setup
- Testbeds
- Really Useful Stuff
- Digilent Arty
- CircuitJS experiments
- ASIC Timing and Design flow resources
Getting Started
This section is primarily a series of useful links found online
Is Open Source Hardware Profitable?
RaptorCS on FOSS Hardware Interview
OpenPOWER ISA
Overview of the user ISA:
OpenPOWER OpenFSI Spec (2016)
JTAG
-
Abstract
"The objective of this work is to design and implement a TAP controller IP core compatible with IEEE 1149.1-2013 revision of the standard. The test logic architecture also includes the Test Mode Persistence controller and its associated logic. This work is expected to serve as a ready to use module that can be directly inserted in to a new digital IC designs with little modifications."
RISC-V Instruction Set Architecture
PLEASE UPDATE - we are no longer implementing full RISCV, only user-space RISCV
The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name of the project implies, we will be following the RISC-V ISA I due to it being open-source and also because of the huge software and hardware ecosystem building around it. There are other open-source ISAs but none of them have the same momentum and energy behind it as RISC-V.
To fully take advantage of the RISC-V ecosystem, it is important to be compliant with the RISC-V standards. Doing so will allow us to to reuse most software as-is and avoid major forks.
- [Official compiled PDFs of RISC-V ISA Manual] (https://github.com/riscv/riscv-isa-manual/releases/latest)
- Working draft of the proposed RISC-V Bitmanipulation extension
- RISC-V "V" Vector Extension
- RISC-V Supervisor Binary Interface Specification
Note: As far as I know, we aren't using the RISC-V V Extension directly at the moment. However, there are many wiki pages that make a reference to the V extension so it would be good to include it here as a reference for comparative/informative purposes with regard to Simple-V.
Radix MMU
D-Cache
D-Cache Possible Optimizations papers and links
BW Enhancing Shared L1 Cache Design research done in cooperation with AMD
- Youtube video PACT 2020 - Analyzing and Leveraging Shared L1 Caches in GPUs
- Url to PDF of paper on author's website (clicking will download the pdf)
RTL Arithmetic SQRT, FPU etc.
Sqrt
CORDIC and related algorithms
- https://bugs.libre-soc.org/show_bug.cgi?id=127 research into CORDIC
- https://bugs.libre-soc.org/show_bug.cgi?id=208
- BKM (log(x) and ex)
- CORDIC
- Does not have an easy way of computing tan(x)
- zipcpu CORDIC
- Low latency and Low error floating point TCORDIC (email Michael or Cole if you don't have IEEE access)
- http://www.myhdl.org/docs/examples/sinecomp/ MyHDL version of CORDIC
IEEE Standard for Floating-Point Arithmetic (IEEE 754)
Almost all modern computers follow the IEEE Floating-Point Standard. Of course, we will follow it as well for interoperability.
- IEEE 754-2019: https://standards.ieee.org/standard/754-2019.html
Note: Even though this is such an important standard used by everyone, it is unfortunately not freely available and requires a payment to access. However, each of the Libre RISC-V members already have access to the document.
Among other things, has a nice explanation on arithmetic, rounding modes and the sticky bit.
Nice resource on rounding errors (ulps and epsilon) and the "table maker's dilemma".
Past FPU Mistakes to learn from
- Intel Underestimates Error Bounds by 1.3 quintillion on Random ASCII – tech blog of Bruce Dawson
- Intel overstates FPU accuracy 06/01/2013
Khronos Standards
The Khronos Group creates open standards for authoring and acceleration of graphics, media, and computation. It is a requirement for our hybrid CPU/GPU to be compliant with these standards as well as with IEEE754, in order to be commercially-competitive in both areas: especially Vulkan and OpenCL being the most important. SPIR-V is also important for the Kazan driver.
Thus the zfpacc proposal has been created which permits runtime dynamic switching between different accuracy levels, in userspace applications.
- SPIR-V 1.5 Specification Revision 1
- SPIR-V OpenCL Extended Instruction Set
- SPIR-V GLSL Extended Instruction Set
- OpenCL 2.2 API Specification
- OpenCL 2.2 Extension Specification
OpenCL released the proposed OpenCL 3.0 spec for comments in april 2020
- Announcement video slides (PDF)
Note: We are implementing hardware accelerated Vulkan and OpenCL while relying on other software projects to translate APIs to Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software.
Graphics and Compute API Stack
I found this informative post that mentions Kazan and a whole bunch of other stuff. It looks like many APIs can be emulated on top of Vulkan, although performance is not evaluated.
https://synappsis.wordpress.com/2017/06/03/opengl-over-vulkan-dev/
Pixilica is heading up an initiative to create a RISC-V graphical ISA
3D Graphics Texture compression software and hardware
Various POWER Communities
- An effort to make a 100% Libre POWER Laptop The T2080 is a POWER8 chip.
- Power Progress Community Supporting/Raising awareness of various POWER related open projects on the FOSS community
- OpenPOWER Promotes and ensure compliance with the Power ISA amongst members.
- OpenCapi High performance interconnect for POWER machines. One of the big advantages of the POWER architecture. Notably more performant than PCIE Gen4, and is designed to be layered on top of the physical PCIE link.
- OpenPOWER “Virtual Coffee” Calls Truly open bi-weekly teleconference lines for anybody interested in helping advance or adopting the POWER architecture.
Conferences
Free Silicon Conference
The conference brought together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference covered the full spectrum of the design process, from system architecture, to layout and verification.
https://wiki.f-si.org/index.php/FSiC2019#Foundries.2C_PDKs_and_cell_libraries
LIP6's Coriolis - a set of backend design tools: https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/
Note: The rest of LIP6's website is in French, but there is a UK flag in the corner that gives the English version.
- KLayout - Layout viewer and editor: https://www.klayout.de/
The OpenROAD Project
OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source layout generation flow (RTL-to-GDS).
Other RISC-V GPU attempts
TODO: Get in touch and discuss collaboration
Tests, Benchmarks, Conformance, Compliance, Verification, etc.
RISC-V Tests
RISC-V Foundation is in the process of creating an official conformance test. It's still in development as far as I can tell.
- //TODO LINK TO RISC-V CONFORMANCE TEST
IEEE 754 Testing/Emulation
IEEE 754 has no official tests for floating-point but there are well-known third party tools to check such as John Hauser's TestFloat.
There is also his SoftFloat library, which is a software emulation library for IEEE 754.
Jacob is also working on an IEEE 754 software emulation library written in Rust which also has Python bindings:
- Source: https://salsa.debian.org/Kazan-team/simple-soft-float
- Crate: https://crates.io/crates/simple-soft-float
- Autogenerated Docs: https://docs.rs/simple-soft-float/
A cool paper I came across in my research is "IeeeCC754++ : An Advanced Set of Tools to Check IEEE 754-2008 Conformity" by Dr. Matthias Hüsken.
- Direct link to PDF: http://elpub.bib.uni-wuppertal.de/servlets/DerivateServlet/Derivate-7505/dc1735.pdf
Khronos Tests
OpenCL Conformance Tests
Vulkan Conformance Tests
MAJOR NOTE: We are not allowed to say we are compliant with any of the Khronos standards until we actually make an official submission, do the paperwork, and pay the relevant fees.
Formal Verification
Formal verification of Libre RISC-V ensures that it is bug-free in regards to what we specify. Of course, it is important to do the formal verification as a final step in the development process before we produce thousands or millions of silicon.
Possible way to speed up our solvers for our formal proofs https://web.archive.org/web/20201029205507/https://github.com/eth-sri/fastsmt
Algorithms (papers) submitted for 2018 International SAT Competition https://web.archive.org/web/20201029205239/https://helda.helsinki.fi/bitstream/handle/10138/237063/sc2018_proceedings.pdf https://web.archive.org/web/20201029205637/http://www.satcompetition.org/
Some learning resources I found in the community:
- ZipCPU: http://zipcpu.com/ ZipCPU provides a comprehensive tutorial for beginners and many exercises/quizzes/slides: http://zipcpu.com/tutorial/
- Western Digital's SweRV CPU blog (I recommend looking at all their posts): https://tomverbeure.github.io/
- https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html
- https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html
Automation
LLVM
Adding new instructions:
Branch Prediction
Python RTL Tools
- Migen - a Python RTL
- LiTeX An SOC builder written in Python Migen DSL. Allows you to generate functional RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support, and parameterizeable CSRs.
- Migen Tutorial
- There is a great guy, Robert Baruch, who has a good tutorial on nMigen. He also build an FPGA-proven Motorola 6800 CPU clone with nMigen and put the code and instructional videos online.
- Minerva An SOC written in Python nMigen DSL
- Minerva example using nmigen-soc https://github.com/jfng/minerva-examples/blob/master/hello/core.py
- Using our Python Unit Tests(old)
- https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html
- http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf
Other
- https://wiki.f-si.org/index.php/FSiC2019
- https://fusesoc.net
- https://www.lowrisc.org/open-silicon/
- http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html pipeline skid buffer
- https://pyvcd.readthedocs.io/en/latest/vcd.gtkw.html GTKwave
- http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf Synchronous Resets? Asynchronous Resets? I am so confused! How will I ever know which to use? by Clifford E. Cummings
- http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog, by Clifford E. Cummings In particular, see section 5.8.2: Multi-bit CDC signal passing using 1-deep / 2-register FIFO synchronizer.
- http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-143.pdf Understanding Latency Hiding on GPUs, by Vasily Volkov
- Efabless "Openlane" https://github.com/efabless/openlane
- Co-simulation plugin for verilator, transferring to ECP5 https://github.com/vmware/cascade
- Multi-read/write ported memories https://tomverbeure.github.io/2019/08/03/Multiport-Memories.html
- Data-dependent fail-on-first aka "Fault-tolerant speculative vectorisation" https://arxiv.org/pdf/1803.06185.pdf
- OpenPOWER Foundation Membership https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/
- Clock switching (and formal verification) https://zipcpu.com/formal/2018/05/31/clkswitch.html
- Circuit of Compunit http://home.macintosh.garden/~mepy2/libre-soc/comp_unit_req_rel.html
- Circuitverse 16-bit https://circuitverse.org/users/17603/projects/54486
Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance. https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf
Real/Physical Projects
- https://chips4makers.io/blog/
- https://hackaday.io/project/7817-zynqberry
- https://github.com/efabless/raven-picorv32
- https://efabless.com
- https://efabless.com/design_catalog/default
- https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless
- https://mshahrad.github.io/openpiton-asplos16.html
ASIC tape-out pricing
Funding
Good Programming/Design Practices
- Liskov Substitution Principle
- Principle of Least Astonishment
- https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16
- http://flopoco.gforge.inria.fr/
- Fundamentals of Modern VLSI Devices https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ
12 skills summary
Analog Simulation
- https://github.com/Isotel/mixedsim
- http://www.vlsiacademy.org/open-source-cad-tools.html
- http://ngspice.sourceforge.net/adms.html
- https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations
Libre-SOC Standards
This list auto-generated from a page tag "standards":
Server setup
Testbeds
Really Useful Stuff
- https://github.com/im-tomu/fomu-workshop/blob/master/docs/requirements.txt
- https://github.com/im-tomu/fomu-workshop/blob/master/docs/conf.py#L39-L47
Digilent Arty
- https://store.digilentinc.com/pmod-sf3-32-mb-serial-nor-flash/
- https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/
- https://store.digilentinc.com/pmod-vga-video-graphics-array/
- https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
- https://store.digilentinc.com/pmod-rtcc-real-time-clock-calendar/
- https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/