Sunday, 2021-07-11

*** craigoverend[m] <craigoverend[m]!~craigover@2001:470:69fc:105::12bc> has left #libre-soc10:30
lkclvery interesting article about RISC-V
lkclprogrammerjake: do refer sasi to that, as well as adrian_b's ycombinator if you see them20:23
programmerjakehmm, I don't have the ycombinator link...can you post it?20:36
rscInteresting. Is there also a comparision between OpenPOWER and (ARM|RISC-V)?20:41
rsc(not that I would understand that much, but a bit at least)20:41
lkclrsc: i did one in the CINECA2021 video, 1 sec21:00
programmerjakethat risc-v comparison looks pretty good, though there are some mistakes, such as the entry about changing FP rounding modes requiring a full pipe fence, RISC-V specifically has separate control and status CSR views to prevent that exact issue21:00
lkclyes, it was an early draft he reviewed21:01
lkclbut erincandescent noticed the same thing that adrian_b did21:01
lkclyes i just remembered that, doh :021:01
programmerjakealso, she updated it for spec version 2.221:02
lkclrsc, found it.  ISC2021 not CINECA2021
lkclit's basically the same thing: no Condition Codes (OpenPOWER has those)21:02
lkclno Indexed LD/ST modes (OpenPOWER has those)21:03
lkclno LD/ST-with-shift (OpenPOWER *doesn't* have those)21:03
lkclFP branch-and-compare you actually have to do the compare into an *integer* register... and then do a BEQ on the *integer* register21:04
lkclwe seriously dodged a bullet here.21:04

Generated by 2.17.1 by Marius Gedminas - find it at!