| *** craigoverend[m] <craigoverend[m]!~craigover@2001:470:69fc:105::12bc> has left #libre-soc | 10:30 | |
| lkcl | very interesting article about RISC-V https://gist.github.com/erincandescent/8a10eeeea1918ee4f9d9982f7618ef68 | 20:23 |
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| lkcl | programmerjake: do refer sasi to that, as well as adrian_b's ycombinator if you see them | 20:23 |
| programmerjake | hmm, I don't have the ycombinator link...can you post it? | 20:36 |
| rsc | Interesting. Is there also a comparision between OpenPOWER and (ARM|RISC-V)? | 20:41 |
| rsc | (not that I would understand that much, but a bit at least) | 20:41 |
| lkcl | https://news.ycombinator.com/item?id=24459314 | 20:59 |
| lkcl | rsc: i did one in the CINECA2021 video, 1 sec | 21:00 |
| programmerjake | that risc-v comparison looks pretty good, though there are some mistakes, such as the entry about changing FP rounding modes requiring a full pipe fence, RISC-V specifically has separate control and status CSR views to prevent that exact issue | 21:00 |
| lkcl | yes, it was an early draft he reviewed | 21:01 |
| programmerjake | *she* | 21:01 |
| lkcl | but erincandescent noticed the same thing that adrian_b did | 21:01 |
| lkcl | yes i just remembered that, doh :0 | 21:01 |
| programmerjake | also, she updated it for spec version 2.2 | 21:02 |
| lkcl | rsc, found it. ISC2021 not CINECA2021 https://youtu.be/kVT31txMBQo?t=391 | 21:02 |
| lkcl | it's basically the same thing: no Condition Codes (OpenPOWER has those) | 21:02 |
| lkcl | no Indexed LD/ST modes (OpenPOWER has those) | 21:03 |
| lkcl | no LD/ST-with-shift (OpenPOWER *doesn't* have those) | 21:03 |
| lkcl | FP branch-and-compare you actually have to do the compare into an *integer* register... and then do a BEQ on the *integer* register | 21:04 |
| lkcl | we seriously dodged a bullet here. | 21:04 |
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