SPRs

Note OpenPOWER v3.1 p12:

 The designated SPR sandbox consists of non-privileged SPRs
 704-719 and privileged SPRs 720-735.

There are five SPRs, available in any privilege level:

  • MVL (the Maximum Vector Length)
  • VL (which has different characteristics from standard SPRs)
  • SUBVL (effectively a kind of Packed SIMD of size 2, 3 or 4)
  • SVSTATE (containing copies of MVL, VL and SUBVL as well as context information)
  • SVSRR0 which is used for exceptions and traps to store SVSTATE.

MVL, VL and SUBVL are only provided for convenience: normally setvl would be used to obtain a copy of VL, for example.

For Privilege Levels (trap handling) there are the following SPRs, where x may be u, s or h for User, Supervisor or Hypervisor Modes respectively:

  • (x)eSTATE (useful for saving and restoring during context switch, and for providing fast transitions)

The u/s SPRs are treated and handled exactly like their (x)epc equivalents. On entry to or exit from a privilege level, the contents of its (x)eSTATE are swapped with SVSTATE.

MAXVECTORLENGTH (MVL)

MAXVECTORLENGTH is the same concept as MVL in RVV, except that it is variable length and may be dynamically set. MVL is however limited to the regfile bitwidth, 64.

Vector Length (VL)

VSETVL is slightly different from RVV. Similar to RVV, VL is set to be within the range 0 <= VL <= MVL (where MVL in turn is limited to 1 <= MVL <= XLEN)

VL = rd = MIN(vlen, MVL)

where 1 <= MVL <= XLEN

SUBVL - Sub Vector Length

This is a "group by quantity" that effectively asks each iteration of the hardware loop to load SUBVL elements of width elwidth at a time. Effectively, SUBVL is like a SIMD multiplier: instead of just 1 operation issued, SUBVL operations are issued.

The main effect of SUBVL is that predication bits are applied per group, rather than by individual element. Legal values are 1 to 4. Illegal values raise an exception.

SVSTATE

This is a standard SPR that contains sufficient information for a full context save/restore (see SVSRR0). It contains (and permits setting of):

  • MVL
  • VL
  • dststep - the destination element offset of the current parallel instruction being executed
  • srcstep - for twin-predication, the source element offset as well.
  • SUBVL
  • svstep - the subvector element offset of the current parallel instruction being executed
  • vfirst - Vertical First mode. srcstep, dststep and substep do not advance unless explicitly requested to do so with pseudo-op svstep (a mode of setvl)
  • RMpst - REMAP persistence. REMAP will apply only to the following instruction unless this bit is set, in which case REMAP "persists". Reset (cleared) on use of the setvl instruction if used to alter VL or MVL.
  • hphint - Horizontal Parallelism Hint. In Vertical First Mode hardware MAY perform up to this many elements in parallel per instruction. Set to zero to indicate "no hint".
  • SVme - REMAP enable bits, indicating which register is to be REMAPed. RA, RB, RC, RT or EA.
  • mi0-mi4 - when the corresponding SVme bit is enabled, mi0-mi4 indicate the SVSHAPE (0-3) that the corresponding register (RA etc) should use.

For hphint, the number chosen must be consistently executed every time. Hardware is not permitted to execute five computations for one instruction then three on the next. hphint is a hint from the compiler to hardware that up to this many elements may be safely executed in parallel. Interestingly, when hphint is set equal to VL, it is in effect as if Vertical First mode were not set, because the hardware is given the option to run through all elements in an instruction. This is exactly what Horizontal-First is: a for-loop from 0 to VL-1 except that the hardware may choose the number of elements.

Note to programmers: changing VL during the middle of such modes should be done only with due care and respect for the fact that SVSTATE has exactly the same peer-level status as a Program Counter.

The format of the SVSTATE SPR is as follows:

Field Name Description
0:6 maxvl Max Vector Length
7:13 vl Vector Length
14:20 srcstep for srcstep = 0..VL-1
21:27 dststep for dststep = 0..VL-1
28:29 subvl Sub-vector length
30:31 svstep for svstep = 0..SUBVL-1
32:33 mi0 REMAP RA SVSHAPE0-3
34:35 mi1 REMAP RB SVSHAPE0-3
36:37 mi2 REMAP RC SVSHAPE0-3
38:39 mo0 REMAP RT SVSHAPE0-3
40:41 mo1 REMAP EA SVSHAPE0-3
42:46 SVme REMAP enable (RA-RT)
47:54 rsvd reserved
55:61 hphint horizontal parallelism hint
62 RMpst REMAP persistence
63 vfirst Vertical First mode

The relationship between SUBVL and the subvl field is:

SUBVL (29..28)
1 0b00
2 0b01
3 0b10
4 0b11

Notes:

  • The entries are truncated to be within range. Attempts to set VL to greater than MAXVL will truncate VL.
  • Setting srcstep, dststep to 64 or greater, or VL or MVL to greater than 64 is reserved and will cause an illegal instruction trap.

SVSRR0

In scalar v3.0B traps, exceptions and interrupts, two SRRs are saved/restored:

  • SRR0 to store the PC (CIA/NIA)
  • SRR1 to store a copy of the MSR

Given that SVSTATE is effectively a Sub-PC it is critically important to add saving/restoring of SVSTATE as a full peer equal in status to PC, in every way. At any time PC is saved or restored, so is SVSTATE in exactly the same way for exactly the same reasons. Thus, at an exception point, hardware must save/restore SVSTATE in SVSRR0 at exactly the same time that SRR0 is saved/restored in PC and SRR1 in MSR.

The SPR name given for the purposes of saving/restoring SVSTATE is SVSRR0.