# Scalar OpenPOWER Audio and Video Opcodes

the fundamental principle of SV is a hardware for-loop. therefore the first (and in nearly 100% of cases only) place to put Vector operations is first and foremost in the scalar ISA. However only by analysing those scalar opcodes in a SV Vectorization context does it become clear why they are needed and how they may be designed.

This page therefore has accompanying discussion at https://bugs.libre-soc.org/show_bug.cgi?id=230 for evolution of suitable opcodes.

# Audio

The fundamental principle for these instructions is:

• identify the scalar primitive
• assume that longer runs of scalars will have Simple-V vectorizatin applied
• assume that "swizzle" may be applied at the (vec2 - SUBVL=2) Vector level, (even if that involves a mv.swizxle which may be macro-op fused) in order to perform the necessary HI/LO selection normally hard-coded into SIMD ISAs.

Thus for example, where OpenPOWER VSX has vpkswss, this would be achieved in SV with simply:

• applying saturation to minu (sv.minu/satu)
• 1st op, swizzle-selection vec2 "select X only" from source to dest: dest.X = extclamp(src.X)
• 2nd op, swizzle-select vec2 "select Y only" from source to dest dest.Y = extclamp(src.Y)

Macro-op fusion may be used to detect that these two interleave cleanly, overlapping the vec2.X with vec2.Y to produce a single vec2.XY operation.

Alternatively Twin-Predication may be applied, with every even bit set in the source mask and every odd bit set in the destination mask:

``````r3=0b10101010
r10=0b01010101
r0=0x00007fff # or other limit
sv.minu/satu/sm=r3/dm=r10/ew=32 *r20,*r20,r0
``````

## Scalar element operations

• clamping / saturation for signed and unsigned. best done similar to FP rounding modes, i.e. with an SPR.
• average-add. result = (src1 + src2 + 1) >> 1
• abs-diff: result = (src1 > src2) ? (src1-src2) : (src2-src1)
• signed min/max

[un]signed min/max instructions are specifically needed for vector reduce min/max operations which are pretty common.

# VSX SIMD analysis

Useful parts of VSX, and how they might map.

## vpks[*][*]s (vec_pack*)

signed and unsigned, these are N-to-M (N=64/32/16, M=32/16/8) chop/clamp/sign/zero-extend operations. May be implemented by a clamped move to a smaller elwidth.

The other direction, vec_unpack widening ops, may need some way to tell whether to sign-extend or zero-extend.

scalar extsw/b/h gives one set, mv gives another. src elwidth override and dest elwidth override provide the pack/unpack.

implemented by Pack/Unpack. normal arithmetic also has Pack-with-Saturate.

## vavgs* (vec_avg)

signed and unsigned, 8/16/32: these are all of the form:

``````result = truncate((a + b + 1) >> 1))
``````

These do not exist in scalar ISA and would need to be added. Essentially it is a type of post-processing involving the CA bit so could be included in the existing scalar pipeline ALU

## vabsdu* (vec_abs)

unsigned 8/16/32: these are all of the form:

``````result = (src1 > src2) ? truncate(src1-src2) :
truncate(src2-src1)
``````

These do not exist in the scalar ISA and would need to be added

## abs-accumulate

signed and unsigned variants needed:

``````result += (src1 > src2) ? truncate(src1-src2) :
truncate(src2-src1)
``````

These do not exist in the scalar ISA and would need to be added

## vmaxs* / vmaxu* (and min)

signed and unsigned, 8/16/32: these are all of the form:

``````result = (src1 > src2) ? src1 : src2 # max
result = (src1 < src2) ? src1 : src2 # min
``````

These do not exist in the scalar INTEGER ISA and would need to be added. There are additionally no scalar FP min/max, either. These also need to be added.

Also it makes sense for both the integer and FP variants to have Rc=1 modes, where those modes are based on the respective cmp (or fsel / isel) behaviour. In other words, the Rc=1 setting is based on the comparison of the two inputs, rather than on which of the two results was returned by the min/max opcode.

``````result = (src1 > src2) ? src1 : src2 # max
CR0 = CR_computr(src2-src1) # not based on result
``````

## vmerge operations

Their main point was to work around the odd/even multiplies. SV swizzles and mv.x should handle all cases.

these take two src vectors of various widths and splice them together. the best technique to cover these is a simple straightforward predicated pair of mv operations, inverting the predicate in the second case, or, alternately, to use a pair of vec2 (SUBVL=2) swizzled operations.

in the swizzle case the first instruction would be destvec2.X = srcvec2.X and the second would swizzle-select Y: destvec2.Y = srcvec2.Y. macro-op fusion in both the predicated variant and the swizzle variant would interleave the two into the same SIMD backend ALUs (or macro-op fusion identifies the patterns)

with twin predication the elwidth can be overridden on both src and dest such that either straight scalar mv or extsw/b/h can be used to provide the combinations of coverage needed, with only 2 actual instructions (plus vector prefixing)

See mv.vec and mv.swizzle

## Float estimates

``````vec_expte - float 2^x
vec_loge - float log2(x)
vec_re - float 1/x
vec_rsqrte - float 1/sqrt(x)
``````

The spec says the max relative inaccuracy is 1/4096.

In conjunction with the FPSPR "accuracy" bit These could be done by assigning meaning to the "sat mode" SVP64 bits in a FP context. 0b00 is IEEE754 FP, 0b01 is 212 accuracy for FP32. These can be applied to standard scalar FP ops

The other alternative is to use the "single precision" FP operations on a 32-bit elwidth override. As explained in fcvt this halves the precision, operating at FP16 accuracy but storing in a FP32 format.

``````a * b + c
``````

## vec_msum(s) - horizontal gather multiply-add, optionally saturated

This should be separated to a horizontal multiply and a horizontal add. How a horizontal operation would work in SV is TBD, how wide is it, etc.

``````a.x + a.y + a.z ...
a.x * a.y * a.z ...
``````

This would realistically need to be done with a loop doing a mapreduce sequence. I looked very early on at doing this type of operation and concluded it would be better done with a series of halvings each time, as separate instructions: VL=16 then VL=8 then 4 then 2 and finally one scalar. i.e. not an actual part of SV al all. An OoO multi-issue engine would be more than capable of dealing with the Dependencies.

That has the issue that's it's a massive PITA to code, plus it's slow. Plus there's the "access to non-4-offset regs stalls". Even if there's no ready operation, it should be made easier and faster than a manual mapreduce loop.

--

As a mid-solution, 4-element gathers were discussed. 4 elements would also make them useful for pixel packing, not just the general vector gather. This is because OR and ADD are the same operation when bits don't overlap.

``````gather-add: d = a.x + a.y + a.z + a.w
gather-mul: d = a.x * a.y * a.z * a.w
``````

But can the SV loop increment the src reg # by 4? Hmm.

The idea then leads to the opposite operation, a 1-to-4 bit scatter instruction. Like gather, it could be implemented with a normal loop, but it's faster for certain uses.

``````bit-scatter dest, src, bits

bit-scatter rd, rs, 8 # assuming source and dest are 32-bit wide
rd = (rs >> 0 * 8) & (2^8 - 1)
rd+1 = (rs >> 1 * 8) & (2^8 - 1)
rd+2 = (rs >> 2 * 8) & (2^8 - 1)
rd+3 = (rs >> 3 * 8) & (2^8 - 1)
``````

So at the start you have a RGBA packed pixel in one 32-bit register, at the end you have each channel separated into its own register, in the low bits, and ANDed so only the relevant bits are there.

## vec_mul*

There should be both a same-width multiply and a widening multiply. Signed and unsigned versions. Optionally saturated.

``````u8 * u8 = u8
u8 * u8 = u16
``````

For 8,16,32,64, resulting in 8,16,32,64,128.

All of these can be done with SV elwidth overrides, as long as the dest is no greater than 128. SV specifically does not do 128 bit arithmetic. Instead, vec2.X mul-lo followed by vec2.Y mul-hi can be macro-op fused to get at the full 128 bit internal result. Specifying e.g. src elwidth=8 and dest elwidth=16 will give a widening multiply

(Now added `maddedu` which is twin-half 64x64->HI64/LO64 in biginteger)

## vec_rl - rotate left

``````(a << x) | (a >> (WIDTH - x))
``````

Standard scalar rlwinm

## vec_sel - bitwise select

``````(a ? b : c)
``````

This does not exist in the scalar ISA and would need to be added

Interesting operation: Tim.Forsyth's video on Larrabee they added a logical ternary lookup table op, which can cover this and more. similar to crops 2-2 bit lookup.

## vec_splat - scatter

Implemented using swizzle/predicate.

## vec_perm - permute

Implemented using swizzle, mv.x.

## vec_*c[tl]z, vec_popcnt - count leading/trailing zeroes, set bits

Bit counts.

``````ctz - count trailing zeroes