encodings concepts:

  • 24 bits available
  • vectors not applicable thus EXTRA4 may bring 4 bits (CR Fields) quantity 3of for a total of 12 bits. GPR/FPR/VR 3 bits extends VR to 512 regs (!) and GPR/FPR to 256 (!)
  • elwidth src/dest is 2x2 for a total 4 bits
  • single predicate mask (one bit) is 1 for type (GPR/VR and CRfield), 3 for source, totals another 4 bits

totals 20 bits leaving 4 for a "Mode".

  • arithmetic can have saturation (2 bits?)
  • LD/ST-update needs Post-Increment, others incl. SEA (Signed Effective Address) another bit adds CIA for PC-relative

potentially this leaves 2 bits for SUBVL. an advantage of that is that VSX could be over-ridden to have the number of PackedSIMD element operations redefined?