[[!oldstandards ]]

Variable-width Variable-packed SIMD / Simple-V / Parallelism Extension Proposal

OBSOLETE. This document is out of date and involved early ideas and discussions. Go to the up-to-date document

References

• SIMD considered harmful https://www.sigarch.org/simd-instructions-considered-harmful/
• Link to first proposal https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/GuukrSjgBH8
• Recommendation by Jacob Bachmeyer to make zero-overhead loop an "implicit program-counter" https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/vYVi95gF2Mo/SHz6a4_lAgAJ
• Re-continuing P-Extension proposal https://groups.google.com/a/groups.riscv.org/forum/#!msg/isa-dev/IkLkQn3HvXQ/SEMyC9IlAgAJ
• First Draft P-SIMD (DSP) proposal https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/vYVi95gF2Mo
• B-Extension discussion https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/zi_7B15kj6s
• Broadcom VideoCore-IV https://docs.broadcom.com/docs/12358545 Figure 2 P17 and Section 3 on P16.
• Hwacha https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-262.html
• Hwacha https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-263.html
• Vector Workshop http://riscv.org/wp-content/uploads/2015/06/riscv-vector-workshop-june2015.pdf
• Predication https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/XoP4BfYSLXA
• Branch Divergence https://jbush001.github.io/2014/12/07/branch-divergence-in-parallel-kernels.html
• Life of Triangles (3D) https://jbush001.github.io/2016/02/27/life-of-triangle.html
• Videocore-IV https://github.com/hermanhermitage/videocoreiv/wiki/VideoCore-IV-3d-Graphics-Pipeline
• Discussion proposing CSRs that change ISA definition https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/InzQ1wr_3Ak
• Zero-overhead loops https://pdfs.semanticscholar.org/dbaa/66985cc730d4b44d79f519e96ec9c43ab5b7.pdf
• Multi-ported VLIW Register File Implementation https://ce-publications.et.tudelft.nl/publications/1517_multiple_contexts_in_a_multiported_vliw_register_file_impl.pdf
• Fast context save/restore proposal https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/57F823FA.6030701%40gmail.com
• Register File Bank Cacheing https://www.princeton.edu/~rblee/ELE572Papers/MultiBankRegFile_ISCA2000.pdf
• Expired Patent on Vector Virtual Memory solutions https://patentimages.storage.googleapis.com/fc/f6/e2/2cbee92fcd8743/US5895501.pdf
• Discussion on RVV "re-entrant" capabilities allowing operations to be restarted if an exception occurs (VM page-table miss) https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/IuNFitTw9fM/CCKBUlzsAAAJ
• Dot Product Vector https://people.eecs.berkeley.edu/~biancolin/papers/arith17.pdf
• RVV slides 2017 https://content.riscv.org/wp-content/uploads/2017/12/Wed-1330-RISCVRogerEspasaVEXT-v4.pdf
• Wavefront skipping using BRAMS http://www.ece.ubc.ca/~lemieux/publications/severance-fpga2015.pdf
• Streaming Pipelines http://www.ece.ubc.ca/~lemieux/publications/severance-fpga2014.pdf
• Barcelona SIMD Presentation https://content.riscv.org/wp-content/uploads/2018/05/09.05.2018-9.15-9.30am-RISCV201805-Andes-proposed-P-extension.pdf
• http://www.ece.ubc.ca/~lemieux/publications/severance-fpga2015.pdf
• Full Description (last page) of RVV instructions https://inst.eecs.berkeley.edu/~cs152/sp18/handouts/lab4-1.0.pdf
• PULP Low-energy Cluster Vector Processor http://iis-projects.ee.ethz.ch/index.php/Low-Energy_Cluster-Coupled_Vector_Coprocessor_for_Special-Purpose_PULP_Acceleration