[DRAFT] Twin Multiply and Add Doubleword

VA-Form

  • madded RT,RA,RB,RC

Pseudo-code:

<!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
<!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+MAXVL
<!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]
prod[0:127] <- (RA) * (RB)
sum[0:127] <- EXTZ(RC) + prod
RT <- sum[64:127]
RS <- sum[0:63]

Special Registers Altered:

None

[DRAFT] Twin Divide/Modulo Quad Unsigned

VA-Form

  • divmod2du RT,RA,RB,RC

Pseudo-code:

<!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
<!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+MAXVL
<!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]
if ((RC) <u (RB)) & ((RB) != [0]*XLEN) then
    dividend[0:(XLEN*2)-1] <- (RC) || (RA)
    divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)
    result <- dividend / divisor
    modulo <- dividend % divisor
    RT <- result[XLEN:(XLEN*2)-1]
    RS <- modulo[XLEN:(XLEN*2)-1]
    overflow <- 0
else
    overflow <- 1
    RT <- [1]*XLEN
    RS <- [0]*XLEN

Special Registers Altered:

None