Floating Add FFT/DCT [Single]

A-Form

  • ffadds FRT,FRA,FRB (Rc=0)
  • ffadds. FRT,FRA,FRB (Rc=1)

Pseudo-code:

FRT <- FPADD32(FRA, FRB)
FRS <- FPSUB32(FRB, FRA)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI
CR1          (if Rc=1)

Floating Add FFT/DCT [Double]

A-Form

  • ffadd FRT,FRA,FRB (Rc=0)
  • ffadd. FRT,FRA,FRB (Rc=1)

Pseudo-code:

FRT <- FPADD64(FRA, FRB)
FRS <- FPSUB64(FRB, FRA)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI
CR1          (if Rc=1)

Floating Subtract FFT/DCT [Single]

A-Form

  • ffsubs FRT,FRA,FRB (Rc=0)
  • ffsubs. FRT,FRA,FRB (Rc=1)

Pseudo-code:

FRT <- FPSUB32(FRB, FRA)
FRS <- FPADD32(FRA, FRB)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI
CR1          (if Rc=1)

Floating Subtract FFT/DCT [Double]

A-Form

  • ffsub FRT,FRA,FRB (Rc=0)
  • ffsub. FRT,FRA,FRB (Rc=1)

Pseudo-code:

FRT <- FPSUB64(FRB, FRA)
FRS <- FPADD64(FRA, FRB)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI
CR1          (if Rc=1)

Floating Multiply FFT/DCT [Single]

A-Form

  • ffmuls FRT,FRA,FRC (Rc=0)
  • ffmuls. FRT,FRA,FRC (Rc=1)

Pseudo-code:

FRT <- FPMUL32(FRA, FRC)
FRS <- FPMUL32(FRA, FRC, -1)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI
CR1          (if Rc=1)

Floating Multiply FFT/DCT [Double]

A-Form

  • ffmul FRT,FRA,FRC (Rc=0)
  • ffmul. FRT,FRA,FRC (Rc=1)

Pseudo-code:

FRT <- FPMUL64(FRA, FRC)
FRS <- FPMUL64(FRA, FRC, -1)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI
CR1          (if Rc=1)

Floating Divide FFT/DCT [Single]

A-Form

  • ffdivs FRT,FRA,FRB (Rc=0)
  • ffdivs. FRT,FRA,FRB (Rc=1)

Pseudo-code:

FRT <- FPDIV32(FRA, FRB)
FRS <- FPDIV32(FRA, FRB, -1)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI
CR1          (if Rc=1)

Floating Divide FFT/DCT [Double]

A-Form

  • ffdiv FRT,FRA,FRB (Rc=0)
  • ffdiv. FRT,FRA,FRB (Rc=1)

Pseudo-code:

FRT <- FPDIV64(FRA, FRB)
FRS <- FPDIV64(FRA, FRB, -1)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI
CR1          (if Rc=1)

Floating Twin Multiply-Add DCT [Single]

A-Form

  • fdmadds FRT,FRA,FRC,FRB (Rc=0)
  • fdmadds. FRT,FRA,FRC,FRB (Rc=1)

Pseudo-code:

FRS <- FPADD32(FRA, FRB)
sub <- FPSUB32(FRA, FRB)
FRT <- FPMUL32(FRC, sub)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI VXIMZ
CR1          (if Rc=1)

Floating Multiply-Add FFT [Single]

A-Form

  • ffmadds FRT,FRA,FRC,FRB (Rc=0)
  • ffmadds. FRT,FRA,FRC,FRB (Rc=1)

Pseudo-code:

FRT <- FPMULADD32(FRA, FRC, FRB, 1, 1)
FRS <- FPMULADD32(FRA, FRC, FRB, -1, 1)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI VXIMZ
CR1          (if Rc=1)

Floating Multiply-Sub FFT [Single]

A-Form

  • ffmsubs FRT,FRA,FRC,FRB (Rc=0)
  • ffmsubs. FRT,FRA,FRC,FRB (Rc=1)

Pseudo-code:

FRT <- FPMULADD32(FRA, FRC, FRB, 1, -1)
FRS <- FPMULADD32(FRA, FRC, FRB, -1, -1)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI VXIMZ
CR1          (if Rc=1)

Floating Negative Multiply-Add FFT [Single]

A-Form

  • ffnmadds FRT,FRA,FRC,FRB (Rc=0)
  • ffnmadds. FRT,FRA,FRC,FRB (Rc=1)

Pseudo-code:

FRT <- FPMULADD32(FRA, FRC, FRB, -1, -1)
FRS <- FPMULADD32(FRA, FRC, FRB, 1, -1)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI VXIMZ
CR1          (if Rc=1)

Floating Negative Multiply-Sub FFT [Single]

A-Form

  • ffnmsubs FRT,FRA,FRC,FRB (Rc=0)
  • ffnmsubs. FRT,FRA,FRC,FRB (Rc=1)

Pseudo-code:

FRT <- FPMULADD32(FRA, FRC, FRB, -1, 1)
FRS <- FPMULADD32(FRA, FRC, FRB, 1, 1)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI VXIMZ
CR1          (if Rc=1)

Floating SIN [Single]

X-Form

  • fsins FRT,FRB (Rc=0)
  • fsins. FRT,FRB (Rc=1)

Pseudo-code:

FRT <- FPSIN32(FRB)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI VXIMZ
CR1          (if Rc=1)

Floating COS [Single]

X-Form

  • fcoss FRT,FRB (Rc=0)
  • fcoss. FRT,FRB (Rc=1)

Pseudo-code:

FRT <- FPCOS32(FRB)

Special Registers Altered:

FPRF FR FI
FX OX UX XX
VXSNAN VXISI VXIMZ
CR1          (if Rc=1)