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| openpowerbot_ | [slack] <mithro> Anyone here working on the Linux support in LiteX / Microwatt and understand how the interrupt controller works in that case? taylor-bsg was trying to understand it for BlackParrot and LiteEth. I was wondering how it worked for non-RISC-V cpus like MicroWatt / mor1kx | 20:24 |
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| openpowerbot_ | [mattermost] <lkcl> mithro: it's the older-style XICS controller (not the more modern one) | 23:30 |
| openpowerbot_ | [mattermost] <lkcl> which, slightly annoyingly, the full documentation was omitted from release, not for any other reason than nobody has asked before for it | 23:31 |
| openpowerbot_ | [mattermost] <lkcl> ben herrenschmidtt wrote the linux kernel xics driver | 23:31 |
| openpowerbot_ | [mattermost] <lkcl> it's split into two layers: ICS and ICP - Interrupt Controller Session and Interrupt Controller Presentation i presume | 23:32 |
| openpowerbot_ | [mattermost] <lkcl> there's qemu source code which i tracked down | 23:32 |
| openpowerbot_ | [mattermost] <lkcl> and the Libre-SOC core also implements a verbatim-identical version (as in: i literally translated line-for-line the entire xics.vhdl into python) | 23:33 |
| openpowerbot_ | [mattermost] <lkcl> i'll find some links because the links contain the notes about where everything else can be found, 1 sec... | 23:33 |
| openpowerbot_ | [mattermost] <lkcl> https://bugs.libre-soc.org/show_bug.cgi?id=407 | 23:36 |
| openpowerbot_ | [mattermost] <lkcl> XICS is pretty straightforward. edge-triggering is not implemented, but priority is. | 23:39 |
| openpowerbot_ | [mattermost] <lkcl> you get a stack of bits, you hook them up to interrupt wires, you set up the ICS/ICP registers (using ben's xics driver), and blat. | 23:40 |
| openpowerbot_ | [mattermost] <lkcl> Paul: i just got a unit test running showing first instructions executed from virtual memory | 23:42 |
| openpowerbot_ | [mattermost] <lkcl> https://twitter.com/lkcl/status/1472347882623848450 | 23:42 |
| openpowerbot_ | [mattermost] <lkcl> there's been an awful lot of unit testing going on behind that :) | 23:43 |
| openpowerbot_ | [mattermost] <lkcl> dcache.vhdl was ported to dcache.py and had its own unit test in first real-mode | 23:44 |
| openpowerbot_ | [mattermost] <lkcl> icache.vhdl likewies | 23:44 |
| openpowerbot_ | [mattermost] <lkcl> then mmu.vhdl and a basic unit test | 23:44 |
| openpowerbot_ | [mattermost] <lkcl> then we split out the parts of loadstore1.vhdl related to the MMU into its own file | 23:45 |
| openpowerbot_ | [mattermost] <lkcl> then linked all 5 together (dcache, icache, mmu, mmu-FSM and loadstore) and *then* wrote *yet more* unit tests | 23:45 |
| openpowerbot_ | [mattermost] <lkcl> including some cache-misses and deliberate exceptions | 23:45 |
| openpowerbot_ | [mattermost] <lkcl> and theeen - only then - once instruction-fetch-and-miss-and-tlb-load unit test worked - could we even remotely consider actually integrating all that into the TestIssuer core | 23:46 |
| openpowerbot_ | [mattermost] <lkcl> which took 3 days and works great. | 23:46 |
| openpowerbot_ | [mattermost] <lkcl> bottom line is: there's no way in hell we could have gotten to this point without all the fantastic work that everyone has done on microwatt. | 23:47 |
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