openpowerbot_ | [mattermost] <lkcl> mithro: as is usually the case when we port microwatt vhdl to nmigen, a unit test is included which helps aid in understanding. https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/interrupts/xics.py;hb=HEAD | 00:28 |
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openpowerbot_ | [mattermost] <lkcl> Paul, Ben: i've a small favour to ask / idea to suggest. | 05:10 |
openpowerbot_ | [mattermost] <lkcl> i'm running into difficulties getting the simulations to stop "on cue". issuing instructions one at a time stop-start would take forever and not be accurate (no pipeline overlap) | 05:11 |
openpowerbot_ | [mattermost] <lkcl> intrusively inspecting the PC and NIA doesn't work for loops | 05:11 |
openpowerbot_ | [mattermost] <lkcl> the only solution i can think of that meets all the criteria is to add a DMI "stop immediately if you try to execute an instruction at this address" command/register | 05:12 |
openpowerbot_ | [mattermost] <lkcl> which would be pretty much exactly what you'd expect gdb to provide: a hardware breakpoint. | 05:12 |
openpowerbot_ | [mattermost] <lkcl> would that be reasonable to add in microwatt, and can we agree a common DMI address/register/scheme? | 05:14 |
openpowerbot_ | [mattermost] <lkcl> setting an address 0xffffffffffffffff would work as a "disable" because no address can ever have its LSB set | 05:15 |
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openpowerbot_ | [mattermost] <lkcl> well that was pretty easy | 16:00 |
openpowerbot_ | [mattermost] <lkcl> https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=ab2b4fdf732ee48bee76d06a98d613a31312378a | 16:00 |
openpowerbot_ | [mattermost] <lkcl> (and effective) | 16:01 |
openpowerbot_ | [mattermost] <lkcl> now the simulations terminate exactly at the required point, without messing about trying to guess. executing a small loop simulation was particularly problematic because the last instruction was the branch | 16:16 |
openpowerbot_ | [mattermost] <lkcl> and of couuurse, NIA is calculated to be (PC+4), which of couuurse, is outside the size of the simulated-program | 16:17 |
openpowerbot_ | [mattermost] <lkcl> the DMI interface is simply a "storage-point" - a latch - for stop_addr_o (DBGCore.STOPADDR = 0b1011) | 16:18 |
openpowerbot_ | [mattermost] <lkcl> the DMI interface *itself* doesn't do anything with it: the main core however has direct access to it (combinatorially) and simply compares it against the PC (in full) | 16:19 |
openpowerbot_ | [mattermost] <lkcl> so if the LSB of dmi.stop_addr_o is a 1, it can never trigger a halt. | 16:19 |
openpowerbot_ | [mattermost] <lkcl> you can see we're actually *using* the DMI interface in the simulations to start/stop/manage the simulated processor (!) yield from set_dmi(dmi, DBGCore.STOPADDR, len(instructions)*4) | 16:20 |
openpowerbot_ | [mattermost] <lkcl> does that look obvious-enough / short-enough to add to microwatt? | 16:21 |
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