| openpowerbot_ | [mattermost] <lkcl> ben: it turned out to be a *really* obscure nmigen Simulation bug. | 00:15 |
|---|---|---|
| openpowerbot_ | [mattermost] <lkcl> because we have a PLL there is HDL which can run in a different clock domain from the main core | 00:16 |
| openpowerbot_ | [mattermost] <lkcl> but in simulations i make PLL-clock equals Core clock, but still have things-run-from-PLL in a separate domain from things-including-the-core | 00:17 |
| openpowerbot_ | [mattermost] <lkcl> because the assignment of the PLL clock equal to Core clock was just a straight netlist assignment, nmigen simulation was *unable* to perform proper inter-clock-domain synchronisation when "settling" combinatorial logic chains | 00:18 |
| openpowerbot_ | [mattermost] <lkcl> verilator does not have this bug | 00:18 |
| openpowerbot_ | [mattermost] <lkcl> i "solved" the problem by merging the two clock domains during nmigen Simulations. | 00:19 |
| openpowerbot_ | [mattermost] <lkcl> it's a miracle i haven't had more serious problems until now | 00:20 |
| openpowerbot_ | [mattermost] <lkcl> starting tests | 03:55 |
| openpowerbot_ | [mattermost] <lkcl> initialised MMU | 03:55 |
| openpowerbot_ | [mattermost] <lkcl> test 01:PASS | 03:55 |
| openpowerbot_ | [mattermost] <lkcl> test 02:FAIL 1 DAR=0000000000124108 DSISR=0000000040000000 | 03:55 |
| openpowerbot_ | [mattermost] <lkcl> getting there | 03:55 |
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