Sunday, 2022-02-20

openpowerbot[slack] <Matt Johnston> lkcl: ghdl splits byte enables into 8 separate brams too. https://github.com/YosysHQ/yosys/pull/315705:40
openpowerbot[mattermost] <lkcl> matt: nice!11:08
openpowerbot[mattermost] <lkcl> yeah i'm kinda astounded at the resource usage of dcache.vhdl and icache.vhdl on ECP5s.  to fit into a VERSA_ECP5 45k i had to set TLB_SIZE=4, NUM_LINES=4, NUM_WAYS=1 on both11:10
openpowerbot[mattermost] <lkcl> and i have explicit Memory sram declarations in dcache.py and icache.py for sets and cache_rams11:10
openpowerbot[mattermost] <lkcl> Paul: i saw the (relatively) recent commit for popcount to make it multi-cycle, got an idea on that.  had you considered a ROM lookup table similar to how S-boxes for Rijndael are normally done in software?11:12
openpowerbot[mattermost] <lkcl> an 8-bit ROM would (ha ha ironically) likely end up as a BRAM QTY 8 and could potentially cover the first 3 levels of the popcount: 1+1 2+2 4+411:13
openpowerbot[mattermost] <lkcl> matt: the issue i'm encountering is more fundamental - with synth_ecp5, yosys is not correctly identifying opportunities to map to BRAMs *at all*13:57
openpowerbot[mattermost] <lkcl> also the $mem_v2 abstract concept is relatively new in yosys and the various corner-cases (rules for mapping $mem_v2 to BRAMs, SRAMs, or DFFs) haven't quite been sorted out13:59
openpowerbot[mattermost] <lkcl> i managed in libre-soc to successfully identify some explicit opportunities (exactly like where the xilinx synth attribute "distributed" is used) to get yosys to use BRAMs14:00
openpowerbot[mattermost] <lkcl> however some of those triggered the "yeah i can't work out what you mean so i'll leave it as $mem_v2" bug14:00
openpowerbot[mattermost] <lkcl> my point being that trying syn_ramstyle in microwatt vhdl may help14:02
openpowerbot[mattermost] <lkcl> but ironically would potentially cause *more* 8-byte-enable BRAMs to be generated :)14:03

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