| openpowerbot | [mattermost] <lkcl> just looking at this | 15:03 |
|---|---|---|
| openpowerbot | [mattermost] <lkcl> https://github.com/antonblanchard/microwatt/blob/f01f3d233ae4de595fa29beb305d00ce960f041e/soc.vhdl#L542 | 15:03 |
| openpowerbot | [mattermost] <lkcl> and comparing it to page 51 of the Wishbone B4 specification | 15:03 |
| openpowerbot | [mattermost] <lkcl> it looks like stall should *not* be dropped if STB is HI | 15:04 |
| openpowerbot | [mattermost] <lkcl> same on p55 | 15:05 |
| openpowerbot | [mattermost] <lkcl> although, irritatingly, on p50 the text says "stall by slave indicates master should repeat (hold) request" | 15:09 |
| openpowerbot | [mattermost] <lkcl> on p54 it contradicts that by saying "stall by slave indicates master should drop STB" when the accompanying diagram on p55 clearly doesn't do that | 15:09 |
| openpowerbot | [mattermost] <lkcl> given that i'm running into difficulties with stb being dropped early, i suspect this is the cause of the issue | 15:20 |
| openpowerbot | [mattermost] <lkcl> ah. | 19:02 |
| openpowerbot | [mattermost] <lkcl> it's actually deeper non-compliance with the WB4 pipeline spec than just soc.vhdl | 19:03 |
| openpowerbot | [mattermost] <lkcl> this diagram illustrates: | 19:03 |
| openpowerbot | [mattermost] <lkcl> https://ftp.libre-soc.org/2022-03-07_18-57.png | 19:03 |
| openpowerbot | [mattermost] <lkcl> the cut-in diagram on the right is from p51 of the WB4 spec | 19:04 |
| openpowerbot | [mattermost] <lkcl> https://cdn.opencores.org/downloads/wbspec_b4.pdf | 19:04 |
| openpowerbot | [mattermost] <lkcl> on the left shows both i-cache *and* the 64-to-32 downconverter in soc.vhdl dropping stb one clock cycle too early. | 19:05 |
| openpowerbot | [mattermost] <lkcl> s/i-cache/d-cache | 19:05 |
| openpowerbot | [mattermost] <lkcl> i need to check that this is not a bug in dcache.vhdl, because i'm currently using dcache.py... | 19:57 |
| openpowerbot | [mattermost] <lkcl> it's a bug in microwatt. | 19:58 |
| openpowerbot | [mattermost] <lkcl> https://github.com/antonblanchard/microwatt/blob/f01f3d233ae4de595fa29beb305d00ce960f041e/dcache.vhdl#L1553 | 19:58 |
| openpowerbot | [mattermost] <lkcl> although stbs_done should be set, setting r1.wb.stb = 0 should not be | 19:59 |
| openpowerbot | [mattermost] <lkcl> not until cyc is also cleared, a few lines later | 19:59 |
| openpowerbot | [mattermost] <lkcl> which is covered by the ack. | 19:59 |
| openpowerbot | [mattermost] <lkcl> line 1569, also non-WB4-pipeline-compliant, "clear stb when slave accepted request" | 20:03 |
| openpowerbot | [mattermost] <lkcl> if someone could kindly raise a bugreport in the appropriate location, referencing this link, that would be most helpful for everyone that is currently using microwatt | 20:16 |
| openpowerbot | [mattermost] <lkcl> https://libre-soc.org/irclog-microwatt/%23microwatt.2022-03-07.log.html | 20:16 |
| * openpowerbot [mattermost] <lkcl> ponders | 20:17 | |
| openpowerbot | [mattermost] <lkcl> i think i might know why nobody has noticed this before. | 20:17 |
| openpowerbot | [mattermost] <lkcl> soc.vhdl is self-consistent, and has the WB4-to-3 "trick" of setting stall = cyc & ~ack | 20:18 |
| openpowerbot | [mattermost] <lkcl> likewise, in litex, the wrapper joining microwatt deploys the same trick. | 20:19 |
| openpowerbot | [mattermost] <lkcl> that "trick" has the *accidental* side-effect of keeping the non-WB4-pipeline-compliance "at bay" | 20:19 |
| openpowerbot | [mattermost] <lkcl> because by "stall" being set HI (because "ack" has not yet been set), stb is correspondingly always never lowered [when it should not] | 20:19 |
| openpowerbot | [mattermost] <lkcl> however | 20:20 |
| openpowerbot | [mattermost] <lkcl> because i am using nmigen-soc, in a mode that *does* handle stall (i.e. is properly WB4-pipeline-mode compliant) it's why i've been running into difficulties for the past 5 weeks | 20:21 |
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