| openpowerbot | [slack] <Benjamin Herrenschmidt> fun.... tried Vivado 2022.1.2 and we get much more (and worse) timing violations | 01:47 |
|---|---|---|
| openpowerbot | [slack] <Benjamin Herrenschmidt> it regressed 🙂 | 01:48 |
| openpowerbot | [slack] <joel> Which board are you targeting? | 02:01 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> wukong-v2 but that's about the same as arty-100 | 02:18 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> I have both vivado 2019 and 2022 installed side by side so I can compare | 02:18 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> interesting warnings also about the clock constraints generated by litex for liteeth | 02:19 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> it really doesn't like them | 02:19 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> oh well, things to dig into another day, after my trip, no time now | 02:19 |
| openpowerbot | [slack] <Matt Johnston> @Benjamin Herrenschmidt you wouldn't happen to know which litex revision you used to last generate liteeth? | 03:43 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> Not off the top of my head... a while ago for sure, possibly even with some changes of mine in there | 03:46 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> I can probably find my git repo later today | 03:46 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> I noticed it got slower with newer microwatts, I think that's Paul adding a cycle latency to the SOC io bridge | 03:46 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> I was musing how to make that thing pipelined earlier .... I need to look harder into it | 03:46 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> not sure I'll have time before I fly out for 2 weeks though | 03:47 |
| openpowerbot | [slack] <Matt Johnston> that'd be handy, thanks. I've been looking at a few revs around there but the CSR banks keep jumping around | 03:47 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> it's also generally sucky on wukon compared to arty, not sure why (wukon uses a GMII PHY, Arty uses a 100Mb one, maybe some packet loss...) | 03:47 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> yeah ... i would be nice to have the SRAM mapped more directly to the CPU with a full 64-bit width | 03:48 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> I kept the IO bus narrower to help with utilization, esp. on Arty 35T ... and because CSRs are 32-bit wide | 03:48 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> that said liteeth is a pretty weak ethernet controller 🙂 | 03:48 |
| openpowerbot | [slack] <Jeremy Kerr> how have you been managing without an MDIO bus control? | 03:50 |
| openpowerbot | [slack] <Jeremy Kerr> phy just OK by default? | 03:50 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> yeah | 04:59 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> looks like it | 04:59 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> might be worth one day putting a half decent eth in there with DMA 🙂 | 05:00 |
| openpowerbot | [slack] <Jeremy Kerr> is there gateware around? or that's a matter of doing something from scratch? | 05:22 |
| openpowerbot | [slack] <Matt Johnston> right, I can get a liteeth to match current `microwatt.dts` with latest liteeth/litex if I patch the gen script with https://github.com/CodeConstruct/liteeth/commit/08d42a53f6bf56035281bee9c0e922099fb667be | 09:18 |
| openpowerbot | [slack] <cdrx> @Benjamin Herrenschmidt coming to Europe ? | 09:19 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> Yup ! | 09:19 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> I'll be in Strasbourg next week and Dublin the one after, going to Plumbers | 09:20 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> You'll be around? | 09:20 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> Yeah LiteX needs a better way to define CSR layout in a compatible way per platform | 09:21 |
| openpowerbot | [slack] <Matt Johnston> yeah. something in this vague direction where you give it a map of names and addresses to the builder (for regs as well as banks) seems like it could work | 09:22 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> There probably is. The difficulty is always getting the Xilinx timing magic right. For example our current liteeth does things with clocks that latest Vivado doesn't like | 09:22 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> Most of that stuff is black magic to me :-) | 09:22 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> Replied to the wrong thread :-) this is about gateware :-) | 09:23 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> Yup | 09:23 |
| openpowerbot | [slack] <joel> That's a neat fix. Send it along and see what Florent says | 09:55 |
| openpowerbot | [slack] <Matt Johnston> https://github.com/enjoy-digital/liteeth/pull/118 | 10:01 |
| openpowerbot | [slack] <joel> Nice! | 10:04 |
| openpowerbot | [slack] <joel> If he takes the patch we should try to add CI to enforce the layout | 10:04 |
| openpowerbot | [slack] <Matt Johnston> mm yeah | 10:06 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> @Paul Mackerras so I was toying with the idea of a CRTC (with VGA and HDMI backends)... one thing seems very clear to me though, we don't want it to feed off the L2 cache | 23:25 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> it can be quite a lot of bandwidth and will massacre the L2 with throw-away data | 23:25 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> which makes me ponder between options here... I could just gen litedram with an extra port and plumb it via the L2 wrapper as some kind of pass-through | 23:26 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> but it gets messy to have to generate different litedrams with/without video... | 23:27 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> and those ports areally wide... | 23:27 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> another option is to put some of the CRTC logic in the L2 wrapper... configure a base address and it provides the address increment and a 32-bit wide pixel FIFO out with a "reset" input fed on vsync | 23:28 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> that way it can interleave the fetches with the L2 refills... FIFO can be smart and refill when it has 128 bytes free | 23:29 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> finally one could just use normal WB DMAs and add a bit to the WB interconnect for "non cached" accesses... sounds simpler but I think without at least a cache the width of the litedram bus (128b) it will be fairly inefficient & high latency | 23:31 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> that way it can interleave the fetches with the L2 refills... FIFO can be smart and refill when it has 128 bits free | 23:31 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> but then I started thinking that DMAs in general are bad for L2... anything that will "stream" large quantities of data will trash the L2 needlessly... but having a complete bypass will hit the problem mentioned above | 23:32 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> it's almost worth having a per-initiator 128-bit single-line cache... | 23:33 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> so I've started thinking of adding an initiator ID to the widhbone going to litedram | 23:33 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> to do ... just that 🙂 | 23:33 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> (it will need a store-snoop of course) | 23:34 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> any thoughts ? better ideas ? | 23:34 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> which also makes me wonder whether we should move towards something like axi/axi-lite (which is easily bridged to wb if needed) ... with full axi we could do out of order responses but we would need some kind of arbitration for responses | 23:50 |
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