| openpowerbot | [slack] <Benjamin Herrenschmidt> Ok, do I came up with something simpler. I'm adding a non-temporal attribute bit to the main wishbone. DMAs will set it. L2 will treat stores the usual way but will pipeline loads directly into the dram queue (fully pipelined) with a little buffer so consecutive DMA reads from the same ram response don't occupy two slots in the dram queue | 04:07 |
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| openpowerbot | [slack] <Benjamin Herrenschmidt> I need to iron out a few kinks and get some good test benches or it will corrupt sdcards but hopefully should work and not be overly complicated | 04:07 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> I'd love to get rid of cyc so DMA & cpu accesses don't have to wait for each other responses... That would mean tags (at least originator ids) and arbitration on the response bus, which means .. axi :-) or very close to axi lite. That said I don't mind butchering our main wishbone to make it look like axi, as long as we keep the IO and external DMA ones more standard.... Food for thought | 04:33 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> Bah... litesdcard will suck on this because it doesn't pipeline... I wish LiteX did pipelined wb. I'm thinking we should really switch to axi :-) or at least axi lite | 05:44 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> The main issue with axi (and axi lite) is that it doubles the address bus due to separate read and write addr channels which is somewhat wasteful on something like microwatt | 06:05 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> Maybe we could come up with a hybrid :-) axibone :-) | 06:05 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> Single command channel, single response channel, but with tags/initiator IDs and separate handshake, no cyc | 06:09 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> Or maybe even split r/w response ... doesn't matter as much | 06:09 |
| openpowerbot | [slack] <Jeremy Kerr> so my `mw_debug` only works if have the analyser connected to JTAG pins :D | 06:59 |
| openpowerbot | [slack] <Jeremy Kerr> (along with the FTDI adaptor...) | 07:01 |
| openpowerbot | [slack] <Jeremy Kerr> so my `mw_debug` only works if have my logic analyser connected to JTAG pins :D | 07:01 |
| openpowerbot | [slack] <Benjamin Herrenschmidt> That's.... fun | 07:37 |
| openpowerbot | [slack] <Jeremy Kerr> i suspect USB/ground dodginess with the PC | 08:17 |
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