Wednesday, 2020-08-26

lkclhi awygle.  yes, about the "house contract of sale" - offer, exchange, complete22:16
lkclit allows a couple of crucial things to be done.22:16
lkclone is: if the bus has a memory map associated with it, and that you consider part of the "offer" phase, you don't have to tie up the bus waiting for an error message you *know* you are going to get because it's an invalid address22:17
lkclso if you have a "is this address even valid" function, it can be used to answer the "offer" question, "if i *was* to make this request, at this address, *would* it succeed?"22:18
lkclthe second improvement comes when you have either multi-issue, an out-of-order, or a SMP, or, well.. anything-other-than-the-simplest-of-simple-designs22:19
lkclwith an "offer-exchange-complete" bus protocol, you can request things like: "if i were to make a request for this virtual memory-mapped page, *would* it succeed?"22:20
lkcland that becomes extremely important for multi-issue because if there's anything that is operating in parallel, out-of-order, you absolutely cannot have a *future* instruction succeed but an earlier one fail.22:21
lkclso the "offer" part gets you a GUARANTEE that when you move to "exchange-and-complete" phase, it's GOING to work, 100%.22:21
lkclthen, you can do the "offer" parts out-of-order, determine BEFORE any damage is done, which ones will succeed22:22
lkclcheck their order22:22
lkclstop at the one that has a "fail"22:22
lkcland issue all the others, knowing *full well* that even if they're actually actioned out-of-order, you have a 100% GUARANTEE that they will complete22:23
lkclwithout that protocol, you have to do this:22:23
lkcl* issue 2, 3, 4, 5, ... 100 LOAD operations22:24
lkcl* do operation 222:24
lkcl* do operation 322:24
lkclfinally do operation 10022:24
lkcland it *has* to be done in-order, one at a time, taking potentially hundreds of cycles, because you have no idea whether one of them would fail.22:25
awyglehm, ok, that makes sense. so how do you actualize this on top of AXI, and why can't you on top of WB?22:30
lkcli've _heard_ that AXI has "identifiers", i don't know the details22:30
lkclwishbone only has "stb / cyc / ack".22:31
lkclthere is no signal to say "please let me know *if* this read/write operation *would* succeed".22:31
lkclas in: "don't actually do it, just tell me if, *if* you were to do it, *would* you be able to 100% successfully complete it... *WITHOUT* and that's the important bit *WITHOUT* actually doing the request"22:32
lkclwishbone *only* has "do this read, take it or leave it" and "do this write, take it or leave it"22:32
lkclnow, now, now.22:32
lkclit's the game host / scammer protocol :)22:33
lkclonce-in-a-lifetime, give me your answer now, now now22:33
lkclTileLink i understand has some sort of cache coherence protocol, which will also be an "offer / exchange / complete"22:34
lkclit'll be along the lines of, "if i make this cache request *in the future*, will you guarantee to hold that line for me?" kind of thing22:34
lkclit requires additional state, basically, beyond a simple single handshake (stb/ack)22:35
awyglehm. admittedly i'm not especially familiar with AXI but i don't see anything in the spec that maps _directly_ to the kind of "speculative" transaction operations you're describing22:36
lkclfrom what i gather - and bear in mind i've only glanced at code which *sigh* wasn't documented - i believe there is separate "control" protocol messaging separate from "data" read/write?22:38
lkcland that there is space for unique incrementing identifiers, and a guarantee in the protocol that the responses must come back in order22:39
lkcli would imagine that it would be possible to "create" an offer-exchange-complete protocol on _top_ of that "control message passing"22:39
awyglei see22:40
awyglei wonder if it is properly impossible to build such a thing on top of WB, or if one could leverage the seldom-used "tag" portions of the spec to do so22:40
lkclyeah this thought occurred to me22:40
lkclmaybe... to use/abuse the... what was it... have to open the WB4 spec PDF...22:41
lkclsection 3.1.622:41
lkclcreate a signal that's tagged as cycle or something22:42
lkclhowever even when looking at the rules for the different types22:42
lkclyou have to obey the protocol rules for that tag type22:42
lkclanything tagged as "address", you are *only* allowed to raise it at the same time as wb.adr22:43
lkclanything tagged "dat_i" you are *only* allowed to raise it at the same time as wb.dat_r (?)22:44
lkcland, well, basically, that just doesn't fit with the idea of having a "control channel".22:44
lkcl*unless*.... :)22:44
lkcl... you actually *use* a completely separate actual wishbone bus *as* a control channel :)22:44
lkcl... or....22:45
lkclyou have an entirely new wire, "this_is_a_control_channel_message" wire22:45
lkcland from then on you can start doing anything you like.22:46
lkclhmmm yeah i think that would work.22:50

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