| cesar[m] | I wonder if you could multiplex several logical Wishbone buses on top of a "augmented" physical Wishbone bus. | 00:32 |
|---|---|---|
| cesar[m] | Each logical Wishbone signal, like ACK, would be qualified by a logical bus identifier. | 00:33 |
| cesar[m] | If a logical bus is frozen, waiting for an ACK, you could still move forward by using another logical bus. | 00:34 |
| cesar[m] | As for speculative confirmation or cancellation of a transaction, I think the outgoing port could simply avoid launching the transaction on the Wishbone bus until confirmed by the source. Since there are multiple logical buses, this would not prevent further transfers. | 01:06 |
| lkcl_ | cesar[m], that's an idea. the bus "identifier" would qualify as a "cycle" tag (section 3.1.6, p38 WB4 spec) | 12:29 |
| lkcl_ | about "avoiding launching the WB transaction until confirmed by the source", what protocol and what bus do you use to communicate on *before* that stage? :) | 12:30 |
| lkcl_ | i mean, you don't _have_ to have a protocol (or a bus) but i can foresee that if one doesn't exist then people will end up inventing one :) | 12:31 |
| *** lkcl_ is now known as lkcl | 14:22 | |
| *** cesar[m] <cesar[m]!cstraussma@gateway/shell/matrix.org/x-gvgtybxztahmnfzu> has left #libre-soc | 23:55 | |
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