| *** lkcl__ is now known as lkcl | 13:12 | |
| * lkcl got a question about how many pipeline stages libre-soc has | 16:17 | |
| lkcl | it's intended as an out-of-order design, so the answer is, strictly, "variable" | 16:18 |
|---|---|---|
| lkcl | there's actually multiple completely separate and distinct pipelines and FSMs (DIV is a blocking FSM at the moment, hidden behind ready/valid/ack/busy API that makes it *look* like another pipeline) | 16:19 |
| lkcl | because of the OoO design, the fact that pipelines take different amounts of time to complete (or aren't in fact pipelines *at all*) is utterly irrelevant | 16:19 |
| lkcl | :) | 16:19 |
| lkcl | MUL is 3-stage, DIV is a FSM and completes in... 64, i think. ALU is 2-stage, Logical is 2-stage, TRAP, SPR and BRANCH are 1-stage. ShiftRot is 2-stage | 16:21 |
| lkcl | and there's a *massive* internal fan-out on that, connecting to the different regfiles. it's a *17* way fan-out for the INT regfile (RA, RB, RC, RS) because some pipelines like Logical only need RA/RB, however ShiftRot needs RA, RB and RS. | 16:23 |
| DaKnig | how many clocs does the libre-soc chip take for the longest station? | 22:11 |
| DaKnig | clocks* | 22:11 |
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