Saturday, 2020-09-05

lkclthe DIV FSM is going to be the longest, currently i think around... 16? 18?00:02
lkcljacob i think arranged 4 combinatorial phases back-to-back per clock00:02
lkclhowever there's a huge difference between the test chip (180nm) and what will end up in 800 to 1000 mhz silicon00:03
DaKnigoh wow. 16. that's a lot (at least in FPGA)00:03
sorearfor a 64-bit div?  nah00:04
sorearagner fog has a 44-cycle worst case for idiv on zen2 and 97 cycles on coffee lake00:07
sorearrocket generates 1 result bit per cycle00:07
DaKnigok I guess Im not too familiar with the numbers then00:08
soreari'll be pretty surprised if you can hit 1GHz with a 4 bit/cycle divider not using very fancy algorithms00:08
DaKnigwhat algorithm is used there?00:08
lkclsorear: it's unlikely that that (temporary) FSM will end up in the 800/1ghz ASIC.  we've a DIV/SQRT/RSQRT pipeline in place, it's just too big to go into 180nm00:18
lkclDaKnig: the FSM has the "usual" single-bit test-and-shift.  long division converted to a single binary bit00:19
sorearyou have an integer sqrt?00:19
lkclsorear: yes.  sqrt and inverse and div, all in the same pipeline code, to save space.00:19
lkcljacob designed it.00:20
lkclit's fixed point.  FP is done simply by putting the mantissa into it (after converting the mantissa to an int)00:21
DaKnigso you only have a single div pipeline for everything including floats?00:23
lkclDaKnig: the idea is to do that, yes.  not for the 180nm chip though.  no FP there, we don't have time00:24
DaKnigwhen is the deadline?00:24
lkcland yes, through "micro-coding" the idea is to split of the "FP preparation phase" from "actual DIV" from "FP normalisation phase"00:25
lkclend of october00:25
DaKnigah I see00:26
lkclXICS is now functional, runs the microwatt xics.bin unit test program under litex sim.py21:27
*** DaKnig <DaKnig!~pi@unaffiliated/daknig> has left #libre-soc21:36

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