| lkcl | the DIV FSM is going to be the longest, currently i think around... 16? 18? | 00:02 |
|---|---|---|
| lkcl | jacob i think arranged 4 combinatorial phases back-to-back per clock | 00:02 |
| lkcl | however there's a huge difference between the test chip (180nm) and what will end up in 800 to 1000 mhz silicon | 00:03 |
| DaKnig | oh wow. 16. that's a lot (at least in FPGA) | 00:03 |
| sorear | for a 64-bit div? nah | 00:04 |
| sorear | agner fog has a 44-cycle worst case for idiv on zen2 and 97 cycles on coffee lake | 00:07 |
| sorear | rocket generates 1 result bit per cycle | 00:07 |
| DaKnig | ok I guess Im not too familiar with the numbers then | 00:08 |
| sorear | i'll be pretty surprised if you can hit 1GHz with a 4 bit/cycle divider not using very fancy algorithms | 00:08 |
| DaKnig | what algorithm is used there? | 00:08 |
| lkcl | sorear: it's unlikely that that (temporary) FSM will end up in the 800/1ghz ASIC. we've a DIV/SQRT/RSQRT pipeline in place, it's just too big to go into 180nm | 00:18 |
| lkcl | DaKnig: the FSM has the "usual" single-bit test-and-shift. long division converted to a single binary bit | 00:19 |
| sorear | you have an integer sqrt? | 00:19 |
| lkcl | sorear: yes. sqrt and inverse and div, all in the same pipeline code, to save space. | 00:19 |
| lkcl | https://git.libre-soc.org/?p=ieee754fpu.git;a=tree;f=src/ieee754/div_rem_sqrt_rsqrt;hb=HEAD | 00:20 |
| lkcl | jacob designed it. | 00:20 |
| lkcl | it's fixed point. FP is done simply by putting the mantissa into it (after converting the mantissa to an int) | 00:21 |
| DaKnig | so you only have a single div pipeline for everything including floats? | 00:23 |
| lkcl | DaKnig: the idea is to do that, yes. not for the 180nm chip though. no FP there, we don't have time | 00:24 |
| DaKnig | when is the deadline? | 00:24 |
| lkcl | and yes, through "micro-coding" the idea is to split of the "FP preparation phase" from "actual DIV" from "FP normalisation phase" | 00:25 |
| lkcl | end of october | 00:25 |
| DaKnig | ah I see | 00:26 |
| lkcl | XICS is now functional, runs the microwatt xics.bin unit test program under litex sim.py | 21:27 |
| *** DaKnig <DaKnig!~pi@unaffiliated/daknig> has left #libre-soc | 21:36 | |
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