| dcz_ | is Coriolis the name of the actual ASIC design? | 08:48 |
|---|---|---|
| dcz_ | I came across it while looking for any attempts to fit cores onto a FPGA | 08:49 |
| pangelo[m] | coriolis is a toolchain: http://coriolis.lip6.fr | 08:59 |
| pangelo[m] | afaiui it is used to turn a logical design into an actual silicon circuit "schematic" for fabrication | 09:01 |
| lkcl | dcz_: alliance / coriolis2. yes, it goes through a series of steps to create GDS-II files | 09:16 |
| lkcl | it's not for use in programming FPGAs, it's for *making* FPGAs (and other ASICs) | 09:17 |
| dcz_ | ah, what I was wondering is whether there's going to be any FPGA-based testing before the ASIC attempt this year | 09:17 |
| lkcl | dcz: yes! :) | 09:50 |
| lkcl | absolutely. using litex. | 09:50 |
| lkcl | https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/litex/florent/versa_ecp5.py;hb=HEAD | 09:51 |
| lkcl | litex is less than ideal (because it uses migen) however it's the quickest way to get "up and running" at the moment | 09:52 |
| dcz_ | oh, the Versa board is supported by SymbiFlow too | 10:04 |
| lkcl | dcz_, it's one of the (few) that is also entirely libre-licensed toolchains for absolutely everything. | 11:57 |
| lkcl | the ulx3s is also supported, which is one of the only (affordable) ways to get hold of an 85k LUTs ECP5 | 11:57 |
| dcz_ | ulx3s seems out of stock though :S | 15:06 |
| daveshah | Usually these are another option for an 85k ECP5 [albeit no DRAM] but atm they seem to mostly be out of stock too https://www.mouser.co.uk/ProductDetail/Lattice/LFE5UM5G-85F-EVN?qs=w%2Fv1CP2dgqoyj9CgAS78aw== | 15:08 |
| lkcl | oh! when i first saw those i thought there was no actual ECP5 on it :) | 15:35 |
| dcz_ | there's also OrangeCrab https://www.latticesemi.com/products/developmentboardsandkits/orangecrab | 15:52 |
| dcz_ | looks like it could be manufactured with the 85k one, but that would probably need a custom order (the links on the page point to that) | 15:52 |
| daveshah | yeah, unless greg has one lying around with an 85k | 15:53 |
| dcz_ | is FPGA synthesis more harsh on RAM than simulations? | 15:57 |
| dcz_ | in terms of required amount | 15:57 |
| lkcl | dcz: i received sponsorship to get a laptop with 64 GB of RAM, a 2TB NVMe HDD/SSD, and an 8-core 4.8ghz i9 | 18:02 |
| lkcl | which, really, tells you that the answer is "yes" :) | 18:02 |
| lkcl | Xilinx FPGA tools typically take up 12 GB of RAM to compile designs, that's if you *limit* the amount of resources it uses. | 18:03 |
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