| mePy2[m] | Oh | 08:47 |
|---|---|---|
| mePy2[m] | <lkcl "in the 180nm test chip, surpriii"> :D | 08:47 |
| mePy2[m] | <3 if I understood correctly | 08:48 |
| lkcl | mePy2[m], can i ask you a favour, if you see AndriiR do say hello and mention that i'd love to answer their questions, but that can only happen if they stick around in the channel :) | 13:53 |
| lkcl | i switch off "keyboard stealing focus" in hexchat a long time ago because i would be typing in a source code window and suddenly find that because someone mentioned my name now i'm typing in the hexchat window | 13:54 |
| lkcl | so i see irc messages when i check them | 13:54 |
| lkcl | i'll reply here then send the irc logs link, if you see AndriiR here again do ping them with it for me? | 14:06 |
| lkcl | AndriiR: i did gate-level design of electronics circuits as a kid, in the mid 1980s. i hadn't *any* "actual" HDL expertise at all, and just picked it up. | 14:08 |
| lkcl | after staring at microwatt VHDL for 6 months doing porting of it to nmigen, i can now actually write it | 14:08 |
| lkcl | nmigen - which creates in-memory AST "representing" HDL rather than being "an actual language you have to express HDL concepts in and know its syntax" is far, far easier to deal with | 14:09 |
| lkcl | here's a tutorial i wrote which you can go over and get "up and running with some concepts" literally from scratch | 14:10 |
| lkcl | https://libre-soc.org/3d_gpu/tutorial/ | 14:10 |
| mePy2[m] | oh, now I think I understood :) | 14:13 |
| mePy2[m] | I’ll let you/him know | 14:13 |
| lkcl | star :) | 14:15 |
| * lkcl continues writing... | 14:15 | |
| lkcl | 180nm deadline is Dec 2nd. that's booked. we therefore *have* to meet that and be ready | 14:15 |
| lkcl | we'll likely be doing a full code-freeze end of october (2 weeks) so i have to track down interrupt issues | 14:16 |
| lkcl | unlikely that we'll be able to fit an MMU but that's ok | 14:16 |
| lkcl | the core will be "experimental and slow but functional". no caches, only one Function Unit per "group" of operations, these are roughly divided down into OpenPOWER ISA spec v3.0B sections | 14:28 |
| lkcl | also, bear in mind: we have one contributor, Cole, who had no HDL experience whatsoever and it's been possible to guide him to do "useful stuff". i'm happy to guide you through the same process once you've learned the basics. | 14:33 |
| lkcl | and you should definitely join the #nmigen channel and just hang out, and ask questions | 14:36 |
| lkcl | ok that'll be here https://libre-soc.org/irclog/%23libre-soc.2020-10-15.log.html | 14:36 |
| lkcl | mePy2[m]: ^ :) | 14:36 |
| mePy2[m] | Nice 👍 | 14:43 |
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