| protractorpro | It looks like some of your former contributors started their own open PowerPC project https://chipeleven.com/ | 05:11 |
|---|---|---|
| cesar[m]1 | Their code base is not free, since the license forbids commercial use. | 10:22 |
| cesar[m]1 | This means we cannot use any of their code, and vice-versa. | 10:34 |
| cesar[m]1 | I'd go as far as advising to not even look at their source files, to avoid the danger that we end up unintentionally deriving from some part of their code. | 10:43 |
| mePy2[m] | Guys, how can I best make the latch in the comp_unit_req_rel image? Which kind of FF it is? (D latch, SR latch, T, JK, ...) | 13:45 |
| mePy2[m] | lkcl | 13:45 |
| lkcl | it's an SR NOR latch in that diagram | 17:04 |
| lkcl | just put 2 NOR gates with a cross-over, that's pretty standard | 17:04 |
| mePy2[m] | Nice, yeah | 17:05 |
| lkcl | cesar[m]1: it's slightly more than that. michael etc. do not full comprehend copyright law and took jointly-owned copyrighted material and are slapping an alternative license on it without permission | 17:05 |
| mePy2[m] | (I deleted the messages actually, because you already replied to me. But I think you still can see them) | 17:05 |
| lkcl | mePy2[m]: you can't delete messages from IRC :) | 17:06 |
| lkcl | and you can't delete them from the IRC history either (https://libre-soc.org/irclog/) | 17:07 |
| mePy2[m] | Anyway, about the SR latch: how it is linked to the rest? (op is linked to S and the other to the R? Does it work?) | 17:07 |
| mePy2[m] | lkcl: Yeah | 17:08 |
| lkcl | 1 sec the SSL certificate hasn't been renewed, i need to call Alain straight away | 17:08 |
| lkcl | ok sorted. right, where were we | 17:09 |
| lkcl | argh it might be due to timezones, argh | 17:10 |
| lkcl | what was the bugreport number you put the SVG under? | 17:10 |
| lkcl | 442 | 17:10 |
| mePy2[m] | Which FF/Latch to use | 17:11 |
| lkcl | you said "about which SR latch", i need to see the diagram you've put it in | 17:11 |
| mePy2[m] | 442 | 17:11 |
| lkcl | ok inkscape is much better | 17:13 |
| lkcl | ok right SR latches are symmetric | 17:13 |
| lkcl | S and R are only "conventions" that you attach to one or other of the inputs | 17:14 |
| lkcl | the important thing is that you use the correct output and that's what you've done | 17:14 |
| mePy2[m] | Yeah, I am still doing it. (Also that image has an imperfection I shall fix) | 17:15 |
| lkcl | the AND gates btw need to start off as straight sides then have a circular curve at the end | 17:15 |
| mePy2[m] | I cannot do it at the moment unfortunately. | 17:16 |
| lkcl | this is why i suggested using the wikimedia CC images | 17:16 |
| lkcl | because the "look" (conventions) are quite specific and well-defined for over 40 years now | 17:16 |
| lkcl | the OR and NOR look great though, very close to the standard convention | 17:17 |
| lkcl | the AND gates not so much | 17:17 |
| lkcl | this is what an AND gate should look like | 17:17 |
| lkcl | https://en.wikipedia.org/wiki/Logic_gate#/media/File:AND_ANSI_Labelled.svg | 17:17 |
| lkcl | and you can use that directly as-is because it's wikimedia CC licensed | 17:18 |
| lkcl | here is an SR NOR latch diagram you have it pretty close https://sub.allaboutcircuits.com/images/04173.png | 17:19 |
| lkcl | let me try and work out which one is... | 17:19 |
| lkcl | ok "Set" (S) is "Open" | 17:19 |
| lkcl | "Reset" (R) is "close" | 17:20 |
| lkcl | there's a cross-over you can see in that PNG | 17:20 |
| lkcl | S "crosses over" to make Q on the *other* gate go HI | 17:20 |
| lkcl | R "crosses over" to make Q-dashed on the *other* gate go HI | 17:20 |
| lkcl | this is at first very confusing :) | 17:20 |
| lkcl | a quick look shows that michael *might* have started from scratch, including on the power decoder | 17:27 |
| mePy2[m] | lkcl: I copied “as is” from the raster image. | 19:42 |
| mePy2[m] | I do not like the AND gates too | 19:42 |
| mePy2[m] | (Neither the NOR at first lol. Anyway, np I can mod it to make it more “professional”) | 19:43 |
| mePy2[m] | Anyway I was referring to the latches at the left. The ones with the operands (and opcode). Which kind of latches they are? lkcl | 19:45 |
| mePy2[m] | How does the circuit work? lkcl Can you explain me? (If you are available now can we do a quick jitsi meet?) | 21:30 |
| mePy2[m] | I mean, what is the purpose of Go_Read, Go_Write, Issue... | 21:30 |
| mePy2[m] | lkcl: We are waiting for you :) | 22:08 |
| cesar[m]1 | ... in the OpenPower coffe meeting. | 22:09 |
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