| lkcl | mePy2[m]: i can email you Mitch Alsup's book chapters. you'll need to agree to credit Mitch Alsup if you use them anywhere (that was his condition) | 10:47 |
|---|---|---|
| lkcl | mePy2[m]: those are just "register latches". | 10:48 |
| lkcl | yeah apologies folks i wasn't up to speaking with people, major headache for 2 days | 11:02 |
| mePy2[m] | Np | 11:12 |
| mePy2[m] | lkcl: What are those? (Mitch Alsup chapters). | 11:14 |
| mePy2[m] | Anyway, about the image, yeah. I am going to change logic gates with the ones from Wikimedia. | 11:14 |
| lkcl | 2 book chapters that extend James Thornton's book "Design of a Computer" which you can find online by searching for that exact phrase | 12:47 |
| lkcl | what mitch did was to update the circuit diagrams to IEEE standard ones | 12:48 |
| lkcl | because Thornton's book was so early (right at the invention of the silicon-germanium transistor) there *were* no IEEE standards! | 12:48 |
| mePy2[m] | lkcl: I uploaded a revised version of the circuit with the logic ports from Wikimedia. You can find the bug and the image here: https://bugs.libre-soc.org/show_bug.cgi?id=442 | 13:22 |
| lkcl | star | 13:45 |
| lkcl | cool! | 13:47 |
| lkcl | that looks pretty good, doesn't it? | 13:47 |
| mePy2[m] | Yeah :D | 13:47 |
| lkcl | ok so let me know if you're happy to credit Mitch Alsup if you use his book chapters anywhere, and i'll email them to you | 13:48 |
| lkcl | the diagram you're redoing is one of his | 13:48 |
| lkcl | directly out of his book | 13:48 |
| lkcl | except for the 'Read Request' bit, which i added | 13:48 |
| lkcl | he provides the "explanation" that goes with it | 13:49 |
| lkcl | the box-with-arrow is called a "register latch" | 13:50 |
| lkcl | it's basically transparent (data in == data out) as long as the thing-coming-in-the-side is HI | 13:50 |
| lkcl | when that transitions to LO, then whatever was last coming in as "input" will *always* be sent out as output | 13:50 |
| lkcl | however the moment that the thing-at-the-side goes HI again, it turns back into "transparent" | 13:51 |
| lkcl | basically it's a way to capture data | 13:51 |
| lkcl | given that each of the register data-capture-latches are connected to an SR NOR | 13:52 |
| lkcl | that _should_ give you enough information to work it out :) | 13:52 |
| lkcl | note that Issue is connected to SR 1&2 | 13:53 |
| lkcl | Go_Read is connected to SR 2&3 | 13:53 |
| lkcl | Go_Write is connected to SR 3&1 | 13:53 |
| lkcl | and the sequence in which the 3 are "pulled" is always | 13:53 |
| lkcl | Issue | 13:53 |
| lkcl | Go_Read | 13:53 |
| lkcl | Go_Write | 13:53 |
| lkcl | Issue | 13:53 |
| lkcl | Go_Read | 13:53 |
| lkcl | Go_Write | 13:53 |
| mePy2[m] | Thank you very much | 14:02 |
| mePy2[m] | To be honest, yesterday I asked Cesar to explain me how the circuit works and I think I understood | 14:03 |
| mePy2[m] | He told me about the Issue-Go_Read-Go_Write “loop” | 14:04 |
| mePy2[m] | I also showed him a thing... :D | 14:05 |
| mePy2[m] | I am so happy about it I think I am quite jealous of it! xD | 14:05 |
| mePy2[m] | Anyway I did the circuit with `simcirjs` and I tested it. Cesar helped me to check everything worked fine. | 14:06 |
| mePy2[m] | lkcl: Then yes, I would like to have those two chapters. Thank you | 14:23 |
| lkcl | cool! :) | 17:02 |
| lkcl | niiice | 17:02 |
| mePy2[m] | Would you like to see it? :) | 17:03 |
| lkcl | yeyeh :) | 17:06 |
| lkcl | it'll be actually really interesting to see it in action | 17:07 |
| mePy2[m] | http://home.macintosh.garden/~mepy2/libre-soc.html | 17:07 |
| mePy2[m] | Here you have :D | 17:08 |
| lkcl | ooOoo :) | 19:13 |
| lkcl | haha that's brilliant | 19:14 |
| lkcl | ok so basically what happens is, the read-release goes through what's called a "Priority Picker" | 19:15 |
| lkcl | (write release, too) | 19:15 |
| lkcl | that's this diagram here | 19:15 |
| lkcl | https://libre-soc.org/3d_gpu/group_pick_rd_rel.jpg | 19:15 |
| lkcl | and the reason is that, quite obviously, only one CompUnit must be allowed to read from one Register File Port at a time | 19:17 |
| lkcl | and we have multiple CompUnits | 19:17 |
| lkcl | so, the PriorityPicker picks one (and only one) | 19:17 |
| lkcl | and feeds that simultaneously into: | 19:17 |
| lkcl | a) the Regfile "read enable" line | 19:17 |
| lkcl | b) the "Go_Read" signal of our CompUnit, here | 19:18 |
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