Wednesday, 2020-10-28

lkclmePy2[m]: i can email you Mitch Alsup's book chapters.  you'll need to agree to credit Mitch Alsup if you use them anywhere (that was his condition)10:47
lkclmePy2[m]: those are just "register latches".10:48
lkclyeah apologies folks i wasn't up to speaking with people, major headache for 2 days11:02
mePy2[m]lkcl: What are those? (Mitch Alsup chapters).11:14
mePy2[m]Anyway, about the image, yeah. I am going to change logic gates with the ones from Wikimedia.11:14
lkcl2 book chapters that extend James Thornton's book "Design of a Computer" which you can find online by searching for that exact phrase12:47
lkclwhat mitch did was to update the circuit diagrams to IEEE standard ones12:48
lkclbecause Thornton's book was so early (right at the invention of the silicon-germanium transistor) there *were* no IEEE standards!12:48
mePy2[m]lkcl: I uploaded a revised version of the circuit with the logic ports from Wikimedia. You can find the bug and the image here:
lkclthat looks pretty good, doesn't it?13:47
mePy2[m]Yeah :D13:47
lkclok so let me know if you're happy to credit Mitch Alsup if you use his book chapters anywhere, and i'll email them to you13:48
lkclthe diagram you're redoing is one of his13:48
lkcldirectly out of his book13:48
lkclexcept for the 'Read Request' bit, which i added13:48
lkclhe provides the "explanation" that goes with it13:49
lkclthe box-with-arrow is called a "register latch"13:50
lkclit's basically transparent (data in == data out) as long as the thing-coming-in-the-side is HI13:50
lkclwhen that transitions to LO, then whatever was last coming in as "input" will *always* be sent out as output13:50
lkclhowever the moment that the thing-at-the-side goes HI again, it turns back into "transparent"13:51
lkclbasically it's a way to capture data13:51
lkclgiven that each of the register data-capture-latches are connected to an SR NOR13:52
lkclthat _should_ give you enough information to work it out :)13:52
lkclnote that Issue is connected to SR 1&213:53
lkclGo_Read is connected to SR 2&313:53
lkclGo_Write is connected to SR 3&113:53
lkcland the sequence in which the 3 are "pulled" is always13:53
mePy2[m]Thank you very much14:02
mePy2[m]To be honest, yesterday I asked Cesar to explain me how the circuit works and I think I understood14:03
mePy2[m]He told me about the Issue-Go_Read-Go_Write “loop”14:04
mePy2[m]I also showed him a thing... :D14:05
mePy2[m]I am so happy about it I think I am quite jealous of it! xD14:05
mePy2[m]Anyway I did the circuit with `simcirjs` and I tested it. Cesar helped me to check everything worked fine.14:06
mePy2[m]lkcl: Then yes, I would like to have those two chapters. Thank you14:23
lkclcool! :)17:02
mePy2[m]Would you like to see it? :)17:03
lkclyeyeh :)17:06
lkclit'll be actually really interesting to see it in action17:07
mePy2[m]Here you have :D17:08
lkclooOoo :)19:13
lkclhaha that's brilliant19:14
lkclok so basically what happens is, the read-release goes through what's called a "Priority Picker"19:15
lkcl(write release, too)19:15
lkclthat's this diagram here19:15
lkcland the reason is that, quite obviously, only one CompUnit must be allowed to read from one Register File Port at a time19:17
lkcland we have multiple CompUnits19:17
lkclso, the PriorityPicker picks one (and only one)19:17
lkcland feeds that simultaneously into:19:17
lkcla) the Regfile "read enable" line19:17
lkclb) the "Go_Read" signal of our CompUnit, here19:18

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