| cesar[m]1 | New slogan: | 09:37 |
|---|---|---|
| cesar[m]1 | Use Simple-V (on your scalar ISA). It adds a whole new (vector) dimension. | 09:37 |
| lkcl | cesar[m]1: ooOoo :) | 12:01 |
| jon_ | Hi all, I'm Jon and I am trying to develop myself into someone that would be useful toward the vision of the EOMA68. I am currently a student and my University has tasked us with finding hardware security researchers we'd like to hear from this semester. Do any of you have recommendation on who I maybe should request? Bunnie comes to mind but anyone else? | 15:58 |
| awygle | lkcl: sure | 16:15 |
| lkcl | jon_, hi! yes, bunnie would be a good start. btw do join the arm-netbooks mailing list, this project is the development of an SoC | 16:54 |
| lkcl | http://lists.phcomp.co.uk/pipermail/arm-netbook/ | 16:54 |
| lkcl | cesar[m]1: a long while back i also designed 2/3D matrix "shuffling" as well https://libre-soc.org/openpower/sv/remap/ | 16:55 |
| lkcl | i got the concept from Aspex Semiconductors (i used to work for them) | 16:56 |
| * lkcl waves to awygle | 16:56 | |
| lkcl | yes, cesar[m]1 has been doing the formal correctness proof on the actual PartitionedSignal class | 16:56 |
| lkcl | https://git.libre-soc.org/?p=ieee754fpu.git;a=blob;f=src/ieee754/part/formal/proof_partition.py;hb=HEAD | 16:57 |
| lkcl | the tricky bit where we are concerned is here: | 16:58 |
| lkcl | https://git.libre-soc.org/?p=ieee754fpu.git;a=blob;f=src/ieee754/part/partsig.py;h=f09b972a4c93e3a07e1f869c1f9a8ff16952743a;hb=HEAD#l45 | 16:58 |
| lkcl | notice it doesn't derive from Value or UserValue/etc ? | 16:58 |
| awygle | mhm | 16:58 |
| lkcl | and, if you use the standard nmigen.Mux or other operations on it, those know absolutely nothing about the dynamic partitioning. | 16:59 |
| awygle | mhm | 16:59 |
| lkcl | here's how a Mux *should* work if nmigen.Mux "understood" partitioning: | 17:00 |
| lkcl | https://git.libre-soc.org/?p=ieee754fpu.git;a=blob;f=src/ieee754/part_mux/part_mux.py;hb=HEAD | 17:00 |
| lkcl | it's actually a dead-simple for-loop, treat each partition separately | 17:00 |
| lkcl | where the "bool" signal is actually not a bool, it's an *array* of bools (single-bits) | 17:01 |
| lkcl | and you just apply each bit of that not-bool independently to the parts of A and B. | 17:01 |
| lkcl | but | 17:01 |
| lkcl | unless nmigen "understands" this, and allows us to "override" the behaviour of nmigen.Mux, we're hosed. | 17:02 |
| awygle | by which you mean "doomed to using PMux everywhere instead of the built-in language features" | 17:02 |
| lkcl | urrr... | 17:03 |
| * lkcl eurgh yes :) | 17:03 | |
| lkcl | and we can't use m.If, m.Else, m.Switch - nothing | 17:03 |
| lkcl | all of the very features of nmigen that make it attractive: completely prohibited. | 17:03 |
| awygle | right | 17:03 |
| lkcl | hence this: https://bugs.libre-soc.org/show_bug.cgi?id=458#c4 | 17:03 |
| lkcl | which should actually be, if my estimates are right, something less than a 50 line patch | 17:04 |
| lkcl | (first version, that is) | 17:04 |
| awygle | and i assume from this that you are not using an nmigen fork, but are either committed to using or at the very least intend to use upstream | 17:04 |
| lkcl | correct. | 17:04 |
| lkcl | we reaaally do not want to become the permanent maintainers of a high-profile nmigen fork. | 17:05 |
| lkcl | there's one already: that's causing enough problems for whitequark | 17:05 |
| cesar[m]1 | The thing is, both m.If and m.Switch end up as "switch" statements in RTLIL. It is actually Yosys that inserts the MUXes. | 17:05 |
| lkcl | ah: i traced it through, it's ok :) | 17:06 |
| awygle | and so the limiting factor here is "somebody needs to interface with whitequark to get this upstreamed and/or find an equivalent solution, ideally in a way which does not cause either side undue stress" | 17:06 |
| lkcl | awygle: exactly. | 17:06 |
| lkcl | cesar[m]1: fascinatingly, m.If and m.Else end up calling (via a roundabout route), into Value.cases() | 17:06 |
| * lkcl goes to check the name | 17:06 | |
| awygle | and i think you mentioned your timeline in nmigen the other day and it was a single digit number of weeks? | 17:06 |
| lkcl | sorry, matches | 17:07 |
| lkcl | https://github.com/nmigen/nmigen/blob/746886ca8ac3b9a8941b540a347452805acbbcf2/nmigen/hdl/ast.py#L389 | 17:07 |
| lkcl | 3 to 6 weeks, it'll hit the critical path, yes. | 17:08 |
| lkcl | we can delay / extend that somewhat by re-focussing people, say, i do the power-gem5 simulator work | 17:08 |
| cesar[m]1 | BTW, while I see Part being used in bit_select and word_select, I don't see Value.part() anywhere, and don't really see how it could help PartitionedSignal. | 17:09 |
| lkcl | yes, this needs investigation. i tracked it through, part generates slightly different verilog. i think... a shiftx cell rather than a shift cell? something like that? | 17:10 |
| lkcl | awygle: we don't need absolutely everything. | 17:11 |
| lkcl | even just having m.If, m.Else is a massive "win". | 17:11 |
| lkcl | m.Switch is the next highest priority | 17:11 |
| lkcl | if we can't get a parallel version of Cat, that's a pain but not insurmountable, we'll "make do" | 17:12 |
| lkcl | as this is quite important (read: critical) we can allocate quite a substantial budget to it. | 17:14 |
| awygle | i see | 17:14 |
| awygle | well i'm not un-interested, but slightly hesitant because this requires another person's consent for the most obvious deliverable. let me think about it and i'll get back to you soon. | 17:15 |
| lkcl | we can run with a fork for some months. | 17:16 |
| lkcl | appreciated. thank you awygle | 17:16 |
| lkcl | ultimately, though, if whitequark isn't happy to include this, then much as it pains me to say it we'd be forced to fork nmigen. i'd clearly very much prefer that scenario did not occur. | 17:18 |
| awygle | of course | 17:18 |
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