Saturday, 2021-02-06

segherlkcl: hi!13:50
segherafk for a bit now though13:50
*** manuel_ is now known as ManuV14:36
jxj-openwifi[m]hope this the room you mentioned?16:24
lkcljxj-openwifi[m], yes :)16:38
lkclsegher, hi back16:38
lkclwas using smartphone so afk (laptop)16:38
segherhi!  i'll be here in 2h or so16:47
segherlkcl: here?18:23
lxoindeed.  hi segher.  good to see you here20:24
segherhi alex20:24
segherlkcl asked me to explain how XER[SO] is not slow at all on modern cpus, but we seem to have problems with the handshake :-)\20:25
lxouhh...  I suppose the fosdem weekend gets to be a very busy one for everyone20:28
segherheh, it is totally relaxing for me compared to last week :-)20:28
lxoheh, fair enough20:31
segherthis is very first time i actually am at fosdem20:35
segheri have planned to do that for ten years or so already, but it never worked out20:36
Kyrassieryo! i just wanted to ask if you are aware of & & ?21:17
Kyrassieri know it's old, and has been implemented in (32bit) sparc only, and because of the name hard to find if you don't know what you are looking for :-)21:19
Kyrassierso i thought i should let you know of that :-)21:19
Kyrassierjust in case...21:20
* Kyrassier thinks this is a worthy concept to consider, since you seem to almost start from scratch anyway21:23
segherleon3, wow it *is* old!21:23
Kyrassieryes, but proven. anyway, the concept as such is architecture independent21:24
segheryeah, just commenting on the age of this21:24
jxj-openwifi[m]Just curious, have you ever consider spinalHDL?21:32
lkclhooraaay!  phoronix picked up on my "pissing in the back yard" comment!22:27
lkclwe can now put that in the investor memorandom *rotfl* :)22:27
* Kyrassier sighs22:27
lkclsorry folks i needed a rest after a long day22:28
lkclKyrassier: well we needed something to amuse / grab the attention of investors22:28
Kyrassierjust ignore my sighing. i'm just no fan of that site22:29
Kyrassierbecause 'oldfartism', and such 8)22:29
lkclphoronix have been following the project, quite supportively, for a couple of years now22:30
Kyrassiererr, which? libre-soc?22:31
Kyrassierhrrm. maybe i haven't followed phoronix that much. maybe they got 'better'. dunno22:32
jn__is a video recording of the fosdem talk online?22:33
lkcljn__, i pre-uploaded them to youwtyowb, 1 sec22:37
jn__thanks, luke!22:37
KyrassierWTF!? a whole new irc experience with this webchat thingy! it embeds the vids!22:38
* Kyrassier feels old. so old....22:38
lkclKyrassier: lol.  well if it makes you feel better, i'm 50, Alain is over 63, and the Executive Business Team average age is 65 :)22:40
* Kyrassier relaxes a little22:41
lkcljxj-openwifi[m]: we considered spinalHDL and rejected it because it's chisel3.22:41
lkclit took i think about 3 months of comprehensive discussion and review to settle on nmigen22:41
lkclsegher: apologies i needed to rest a bit after a long day22:43
lkclinteresting about microgrids.  reminds me of OpenPITON.22:53
Kyrassieryah. i have that bookmarked for a while. but... this apple-core/microgrid thingy goes further, with just the slightest bit of toolchain support22:56
Kyrassieressentially splitting that was is understood as thread over many ALUs22:57
Kyrassiersounds impossible. i know22:59
lkcloink :)23:01
lkclthat makes me slightly nervous, having been involved in a non-standard processor company called Aspex Microelectronics, back in 200323:02
lkclthey programmed it at the assembly level: productivity was measured in DAYS per line of assembler23:02
segherlkcl: no problem at all...  i just finished watching a film myself23:09
segherlkcl: nmigen is just a new implementation of migen?23:10
jn__a bit of a redesign and reimplementation as far as i understand it23:11
jn__good readme here:
Kyrassierbut... how does one go from nmigen to ASIC?23:12
Kyrassierinstead of FPGA?23:12
segherjn__: i know a lot of people who use migen, i'll ask them about nmigen :-)23:13
segher(i pretty much never write fpga code myself)23:14
lkclsegher, yes it is23:20
segherwant to talk about the SO stuff now?23:20
lkclmigen is basically a thin wrapper around verilog.  it performs absolutely no kind of checking / verification, itself23:20
segheryeah, it is simpler to write than verilog23:21
lkclconsequently we only find some errors during DRC of layout by coriolis2!23:21
segheranyone sane will use vhdl instead, of course23:21
lkclnmigen has some critically important deterministic guarantees23:21
lkcllove to use VHDL... if it had OO inheritance.23:21
lkclsure, let's go over XER.so23:21
segherit is all text, tyou can preprocess it23:22
sorearnmigen wraps yosys RTLIL, which can be turned into verilog or used directly for logic synthesis23:22
segherk.  first, you need to know about XER[OV]23:22
lkclsegher: i successfully implemented XER ov and so in the core23:23
segherXER[OV] is the overlow bit23:23
segherit is set by OE=1 insns23:23
lkcltook a bit of doing, but it works23:23
segherit is very similar to XER[CA]23:23
segherit is only set by some insns23:23
segher(that one, just the carry insns, and sra[wd])23:24
segherXER[SO] is only cleared by mtspr xer, and by mcrxr on old isa implementations23:25
seghermcrxr was lovely (it stores all of CA, OV, SO into a CR field, and clears all those three bits)23:25
segherbut it was very expensive to implement23:25
segher(because it writes all those)23:26
lkcloh interesting.  will look up mcrxr i don't know if it made it into v3.0B23:26
segherso mcrxr was removed in ISA 2.0023:26
segherthere now *is* a mcrxrx again23:26
seghersince 3.0 i think23:27
segherit doesn't clear bits23:27
segherso, many older languages would use SO23:27
segheryou can do many ops, and than after that check if any exception happened23:28
segherjust like you can do with floating point23:28
lkcl - move to / from CRs23:28
segherthere is only one CR23:28
segherCR is the 32-bit register23:28
segheryou mean CR fields23:28
lkclyes, CR fields, sorry23:28
lkclmcrxrx BF ==> CR[4*BF+32:4*BF+35] <-  XER[OV] || XER[OV32] || XER[CA] || XER[CA32]23:29
segherah yes, mxrxrx does ca32 and ov32 as well23:29
segher(those are new in ISA 3.0 as well)23:29
seghermcrxr was exactly XER[0..3]23:30
segherso CA, OV, SO, bit 323:30
segheror is SO bit 3, hrm23:30
segherah no, bit 223:31
segherso OV is cheap to implement23:31
segherjust like CA23:31
segherjust do renamed registers for them, and you're fine23:31
segher(or there are cheaper options even if you can have at most one CA or OV per cycle)23:32
seghera setter of those, i mean23:32
segherbut, SO is very expensive23:32
lkclyehyeh, we're doing reg-rename.  or, will do, down the line23:32
segherany time you do a compare (or a dot insns), you read SO because it is copied to that bit in the CR field!23:32
lkclsigh, yes, because of the inherent read-modify-write cycle23:33
segherno, bit 3 is defined as a copy of the SO for fixed point comparisons23:33
segherso there are very many insns that need to read it23:34
lkclcopy, yes.  so, strictly, you have to read, then modify it, then write (and the CR field, too)23:34
segherno, just read it23:34
segheronly insns that set OV set SO as well23:34
segher(except mtspr 1)23:35
segherand only mtxer can clear SO23:35
lkclright.  yes.  OE=1.  yes, sorry, i was referring to OE=1 operations23:35
segher(since mcrxr no longer exists)23:35
segheryou do not have those in most programs23:36
segherbut you *do* have a lot of comparisons23:36
segheresp. dot insns are frequent23:36
lkclyehyeh.  Paul Mackerras explained that almost nobody does OE=1 outside of unit test suites23:36
lkclyeah i like Rc=123:36
segherit saves an insn23:36
segheri implemented dot insns in GCC many years ago, before i was maintainer, before i worked for IBM even23:37
lkclahh :)23:37
* lkcl much respect :)23:37
segherso, it is really the reading of SO that needs to be sped up23:38
segherwhat is done since power4 is simply to assume it does not change23:38
lkclyes.  ok, so this is why i added a special dedicated regfile for XER bits.23:39
segherand then if the insn is going to complete, it checks if the bit *did* change, and if it did, it flushes23:39
segherit helps to rename CA and OV23:39
segher(if you care about OV :-) )23:39
lkclyes, we'll be able to add reg-renaming (down the line)23:40
segherwhat does "6-bit" mean?23:40
segherfor full_xer23:41
lkclah that's for mcrxrx and friends23:41
segherthat is 4 bits23:41
lkclrather than having to have 3 read ports, we can grab the entire contents (all 3 regs) at once23:41
lkclyyeahh two bits are ignored23:42
seghernot sure what you mean there, heh23:42
lkclthe regfile is 2 bits wide (each port)23:42
segherso this is an ISA 1.xx implementation?23:42
lkclbut only one bit of the register is used23:42
lkclwhere CA and CA32 go into the 2nd 2-bit reg23:43
lkcland OV/OV32 go into the 3rd23:43
lkclit's a v3.0B implementation23:43
lkclwe're mostly tracking microwatt.  sometimes line-for-line23:43
lkclthat way, we get the benefit of Paul and Anton, Mikey and Ben's massive experience23:44
segherdoes benh still work on this?23:44
lkclwhen he can.  he did the... no, mikey did the XICS...23:45
lkclben did... mmm.. the DMI interface in microwatt23:45
lkcland he's been mostly doing the linux kernel patches23:45
lkcli haven't heard from ben for some months23:46
segheri don't see him much either...  last week on irc though :-)23:46
segher(but i just saw he was there...  time zones)23:46
lkcli'm in the UK yet have.. ahh... "adjusted" to waking up somewhere around 12 / 1pm... :)23:48
lkclmy excuse is, "so i can talk to people in the US".  of course, when i visit the US or Canada the exact same thing happens lol23:49
segheri usually have my alarm at 10am...  i'm in .nl, but work US time mostly23:49
segheri often woke up after noon, so i decided to stop doing that23:50
lkclah you're from the netherlands?  i lived in scheveningen, den haag, for 4 years23:50
lkclloved it23:50
segheri'll move to delft soon23:51
segherwalking distance from the hague :-)23:51
lkcli met this guy who used to cycle from rotterdam every day to den haag.  holy s*** could he move.23:52
lkcltried to keep up with him for 7 km... then he said, "ok bye" and added an extra 10km to his speed :)23:53
segherpretty dangerous, cycling fast there, usually23:53
KyrassierNur die Nacht ist edel und gut! Die beste Zeit zum Denken, nichts kann einen ablenken. (Only the night is noble and good. The best time to think, no distraction)23:53
segherthe other traffic doesn't expect you23:53
segherkyrassier: genau :-)23:54
lkclthere's a dedicated cycle path that runs by the side of the freeway, now, from den haag to rotterdam23:54
segheryes, but there are cyclists on it23:54
lkclhaha yes23:54
Kyrassierhow fast could he move?23:55
segher30 or a bit more, i'd guess23:55
Kyrassierlol :)23:55
Kyrassierdepends on the headwind, though23:55
segherthat is easy in .nl23:56
lkclabout 40km/h!!23:56
segheryou *always* have headwind23:56
segherand if you turn around, you still do23:56
Kyrassieryah. i remember23:56
lkcli was able to do around 25 km/h sustained, i was pushing myself to 30 km/h to impress him23:56
segher30 is quite doable with a good bik23:56
lkclyes, he had wheels only 18mm profile (!)23:57
* Kyrassier could do 73 peak for maybe 2 minutes, 60 to 65 on flat grounds for about an hour, and always 50 to 55. oh err, and 45 at 12% uphill,23:58
segherlkcl: wow, most are about 25mm23:58
lkcli bought a Richards S8 from a shop in den haag, it's a semi-custom MTB23:59
Kyrassiernowadays i do 30 to 35 on an old 3-speed without sweat, and if i really push it maybe 4523:59
segher18 is really tiny...  i wonder what pressure that is23:59
lkcli felt safer with MTB slicks and with good brakes23:59
lkcl100 psi23:59
segherand that is?  in real-world units23:59
lkcl90 to 100 psi is normal for racers23:59
segherless than 7atm23:59
segherthat is low23:59

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