| segher | lkcl: hi! | 13:50 |
|---|---|---|
| segher | afk for a bit now though | 13:50 |
| *** manuel_ is now known as ManuV | 14:36 | |
| jxj-openwifi[m] | hello | 16:24 |
| jxj-openwifi[m] | hope this the room you mentioned? | 16:24 |
| lkcl | jxj-openwifi[m], yes :) | 16:38 |
| lkcl | segher, hi back | 16:38 |
| lkcl | was using smartphone so afk (laptop) | 16:38 |
| segher | hi! i'll be here in 2h or so | 16:47 |
| segher | lkcl: here? | 18:23 |
| lxo | https://www.phoronix.com/scan.php?page=news_item&px=LibreSOC-2021 | 18:31 |
| segher | nice | 18:40 |
| lxo | indeed. hi segher. good to see you here | 20:24 |
| segher | hi alex | 20:24 |
| segher | lkcl asked me to explain how XER[SO] is not slow at all on modern cpus, but we seem to have problems with the handshake :-)\ | 20:25 |
| lxo | uhh... I suppose the fosdem weekend gets to be a very busy one for everyone | 20:28 |
| segher | heh, it is totally relaxing for me compared to last week :-) | 20:28 |
| lxo | heh, fair enough | 20:31 |
| segher | this is very first time i actually am at fosdem | 20:35 |
| segher | i have planned to do that for ten years or so already, but it never worked out | 20:36 |
| Kyrassier | yo! i just wanted to ask if you are aware of https://www.jsykora.info/apple-core/ & http://apple-core.info/ & https://web.archive.org/web/20161121135317/http://svp-home.org/microgrids ? | 21:17 |
| Kyrassier | i know it's old, and has been implemented in (32bit) sparc only, and because of the name hard to find if you don't know what you are looking for :-) | 21:19 |
| Kyrassier | so i thought i should let you know of that :-) | 21:19 |
| Kyrassier | just in case... | 21:20 |
| * Kyrassier thinks this is a worthy concept to consider, since you seem to almost start from scratch anyway | 21:23 | |
| Kyrassier | yes? | 21:23 |
| segher | leon3, wow it *is* old! | 21:23 |
| Kyrassier | yes, but proven. anyway, the concept as such is architecture independent | 21:24 |
| segher | yeah, just commenting on the age of this | 21:24 |
| jxj-openwifi[m] | Just curious, have you ever consider spinalHDL? | 21:32 |
| lkcl | hooraaay! phoronix picked up on my "pissing in the back yard" comment! | 22:27 |
| lkcl | we can now put that in the investor memorandom *rotfl* :) | 22:27 |
| * Kyrassier sighs | 22:27 | |
| lkcl | sorry folks i needed a rest after a long day | 22:28 |
| lkcl | Kyrassier: well we needed something to amuse / grab the attention of investors | 22:28 |
| Kyrassier | just ignore my sighing. i'm just no fan of that site | 22:29 |
| Kyrassier | because 'oldfartism', and such 8) | 22:29 |
| lkcl | phoronix have been following the project, quite supportively, for a couple of years now | 22:30 |
| Kyrassier | err, which? libre-soc? | 22:31 |
| lkcl | yeah | 22:31 |
| Kyrassier | hrrm. maybe i haven't followed phoronix that much. maybe they got 'better'. dunno | 22:32 |
| jn__ | is a video recording of the fosdem talk online? | 22:33 |
| lkcl | jn__, i pre-uploaded them to youwtyowb, 1 sec | 22:37 |
| lkcl | https://www.youtube.com/watch?v=7rCeNzrCB_g | 22:37 |
| jn__ | thanks, luke! | 22:37 |
| lkcl | https://www.youtube.com/watch?v=FS6tbfyb2VA | 22:37 |
| Kyrassier | WTF!? a whole new irc experience with this webchat thingy! it embeds the vids! | 22:38 |
| * Kyrassier feels old. so old.... | 22:38 | |
| jn__ | hehe | 22:39 |
| lkcl | Kyrassier: lol. well if it makes you feel better, i'm 50, Alain is over 63, and the Executive Business Team average age is 65 :) | 22:40 |
| Kyrassier | phew! | 22:40 |
| * Kyrassier relaxes a little | 22:41 | |
| lkcl | jxj-openwifi[m]: we considered spinalHDL and rejected it because it's chisel3. | 22:41 |
| lkcl | it took i think about 3 months of comprehensive discussion and review to settle on nmigen | 22:41 |
| lkcl | segher: apologies i needed to rest a bit after a long day | 22:43 |
| lkcl | interesting about microgrids. reminds me of OpenPITON. | 22:53 |
| Kyrassier | yah. i have that bookmarked for a while. but... this apple-core/microgrid thingy goes further, with just the slightest bit of toolchain support | 22:56 |
| Kyrassier | essentially splitting that was is understood as thread over many ALUs | 22:57 |
| Kyrassier | sounds impossible. i know | 22:59 |
| lkcl | oink :) | 23:01 |
| lkcl | that makes me slightly nervous, having been involved in a non-standard processor company called Aspex Microelectronics, back in 2003 | 23:02 |
| lkcl | they programmed it at the assembly level: productivity was measured in DAYS per line of assembler | 23:02 |
| segher | lkcl: no problem at all... i just finished watching a film myself | 23:09 |
| segher | lkcl: nmigen is just a new implementation of migen? | 23:10 |
| jn__ | a bit of a redesign and reimplementation as far as i understand it | 23:11 |
| jn__ | good readme here: https://github.com/nmigen/nmigen | 23:11 |
| Kyrassier | but... how does one go from nmigen to ASIC? | 23:12 |
| Kyrassier | instead of FPGA? | 23:12 |
| segher | jn__: i know a lot of people who use migen, i'll ask them about nmigen :-) | 23:13 |
| segher | (i pretty much never write fpga code myself) | 23:14 |
| lkcl | segher, yes it is | 23:20 |
| segher | want to talk about the SO stuff now? | 23:20 |
| lkcl | migen is basically a thin wrapper around verilog. it performs absolutely no kind of checking / verification, itself | 23:20 |
| segher | yeah, it is simpler to write than verilog | 23:21 |
| lkcl | consequently we only find some errors during DRC of layout by coriolis2! | 23:21 |
| segher | anyone sane will use vhdl instead, of course | 23:21 |
| lkcl | nmigen has some critically important deterministic guarantees | 23:21 |
| lkcl | love to use VHDL... if it had OO inheritance. | 23:21 |
| lkcl | sure, let's go over XER.so | 23:21 |
| segher | it is all text, tyou can preprocess it | 23:22 |
| sorear | nmigen wraps yosys RTLIL, which can be turned into verilog or used directly for logic synthesis | 23:22 |
| segher | k. first, you need to know about XER[OV] | 23:22 |
| lkcl | segher: i successfully implemented XER ov and so in the core | 23:23 |
| segher | XER[OV] is the overlow bit | 23:23 |
| segher | it is set by OE=1 insns | 23:23 |
| lkcl | took a bit of doing, but it works | 23:23 |
| segher | it is very similar to XER[CA] | 23:23 |
| segher | it is only set by some insns | 23:23 |
| segher | (that one, just the carry insns, and sra[wd]) | 23:24 |
| lkcl | https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/common_input_stage.py;hb=HEAD | 23:24 |
| lkcl | https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/common_output_stage.py;hb=HEAD | 23:24 |
| segher | XER[SO] is only cleared by mtspr xer, and by mcrxr on old isa implementations | 23:25 |
| segher | mcrxr was lovely (it stores all of CA, OV, SO into a CR field, and clears all those three bits) | 23:25 |
| segher | but it was very expensive to implement | 23:25 |
| segher | (because it writes all those) | 23:26 |
| lkcl | oh interesting. will look up mcrxr i don't know if it made it into v3.0B | 23:26 |
| segher | so mcrxr was removed in ISA 2.00 | 23:26 |
| segher | there now *is* a mcrxrx again | 23:26 |
| segher | since 3.0 i think | 23:27 |
| segher | it doesn't clear bits | 23:27 |
| lkcl | ahh | 23:27 |
| lkcl | https://github.com/antonblanchard/microwatt/blob/5f8279a14ab2921df91babd684f6a4991c59ac29/decode1.vhdl#L307 | 23:27 |
| segher | so, many older languages would use SO | 23:27 |
| segher | you can do many ops, and than after that check if any exception happened | 23:28 |
| segher | just like you can do with floating point | 23:28 |
| lkcl | https://libre-soc.org/openpower/isa/sprset/ - move to / from CRs | 23:28 |
| segher | there is only one CR | 23:28 |
| segher | CR is the 32-bit register | 23:28 |
| segher | you mean CR fields | 23:28 |
| lkcl | yes, CR fields, sorry | 23:28 |
| segher | k | 23:29 |
| lkcl | mcrxrx BF ==> CR[4*BF+32:4*BF+35] <- XER[OV] || XER[OV32] || XER[CA] || XER[CA32] | 23:29 |
| segher | ah yes, mxrxrx does ca32 and ov32 as well | 23:29 |
| segher | (those are new in ISA 3.0 as well) | 23:29 |
| segher | mcrxr was exactly XER[0..3] | 23:30 |
| segher | so CA, OV, SO, bit 3 | 23:30 |
| segher | or is SO bit 3, hrm | 23:30 |
| segher | ah no, bit 2 | 23:31 |
| segher | aaaanyway | 23:31 |
| segher | so OV is cheap to implement | 23:31 |
| segher | just like CA | 23:31 |
| segher | just do renamed registers for them, and you're fine | 23:31 |
| segher | (or there are cheaper options even if you can have at most one CA or OV per cycle) | 23:32 |
| segher | a setter of those, i mean | 23:32 |
| segher | but, SO is very expensive | 23:32 |
| lkcl | yehyeh, we're doing reg-rename. or, will do, down the line | 23:32 |
| segher | any time you do a compare (or a dot insns), you read SO because it is copied to that bit in the CR field! | 23:32 |
| lkcl | sigh, yes, because of the inherent read-modify-write cycle | 23:33 |
| segher | ? | 23:33 |
| segher | no, bit 3 is defined as a copy of the SO for fixed point comparisons | 23:33 |
| segher | so there are very many insns that need to read it | 23:34 |
| lkcl | copy, yes. so, strictly, you have to read XER.so, then modify it, then write XER.so (and the CR field, too) | 23:34 |
| segher | no, just read it | 23:34 |
| segher | only insns that set OV set SO as well | 23:34 |
| segher | (except mtspr 1) | 23:35 |
| segher | mtxer | 23:35 |
| segher | and only mtxer can clear SO | 23:35 |
| lkcl | right. yes. OE=1. yes, sorry, i was referring to OE=1 operations | 23:35 |
| segher | (since mcrxr no longer exists) | 23:35 |
| segher | k | 23:35 |
| segher | you do not have those in most programs | 23:36 |
| segher | but you *do* have a lot of comparisons | 23:36 |
| segher | esp. dot insns are frequent | 23:36 |
| lkcl | yehyeh. Paul Mackerras explained that almost nobody does OE=1 outside of unit test suites | 23:36 |
| lkcl | yeah i like Rc=1 | 23:36 |
| segher | it saves an insn | 23:36 |
| segher | i implemented dot insns in GCC many years ago, before i was maintainer, before i worked for IBM even | 23:37 |
| lkcl | ahh :) | 23:37 |
| * lkcl much respect :) | 23:37 | |
| segher | so, it is really the reading of SO that needs to be sped up | 23:38 |
| segher | what is done since power4 is simply to assume it does not change | 23:38 |
| lkcl | yes. ok, so this is why i added a special dedicated regfile for XER bits. | 23:39 |
| segher | and then if the insn is going to complete, it checks if the bit *did* change, and if it did, it flushes | 23:39 |
| segher | it helps to rename CA and OV | 23:39 |
| lkcl | https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/regfile/regfiles.py;h=27aaecb9c7268488d807f23a9d0447614765bd47;hb=HEAD#l138 | 23:39 |
| segher | (if you care about OV :-) ) | 23:39 |
| lkcl | yes, we'll be able to add reg-renaming (down the line) | 23:40 |
| segher | what does "6-bit" mean? | 23:40 |
| segher | for full_xer | 23:41 |
| lkcl | ah that's for mcrxrx and friends | 23:41 |
| segher | that is 4 bits | 23:41 |
| lkcl | rather than having to have 3 read ports, we can grab the entire contents (all 3 regs) at once | 23:41 |
| lkcl | yyeahh two bits are ignored | 23:42 |
| lkcl | or | 23:42 |
| segher | not sure what you mean there, heh | 23:42 |
| lkcl | the regfile is 2 bits wide (each port) | 23:42 |
| segher | aha\ | 23:42 |
| segher | so this is an ISA 1.xx implementation? | 23:42 |
| lkcl | but only one bit of the XER.so register is used | 23:42 |
| lkcl | where CA and CA32 go into the 2nd 2-bit reg | 23:43 |
| lkcl | and OV/OV32 go into the 3rd | 23:43 |
| lkcl | it's a v3.0B implementation | 23:43 |
| lkcl | we're mostly tracking microwatt. sometimes line-for-line | 23:43 |
| segher | :-) | 23:43 |
| lkcl | that way, we get the benefit of Paul and Anton, Mikey and Ben's massive experience | 23:44 |
| segher | does benh still work on this? | 23:44 |
| lkcl | when he can. he did the... no, mikey did the XICS... | 23:45 |
| lkcl | ben did... mmm.. the DMI interface in microwatt | 23:45 |
| lkcl | and he's been mostly doing the linux kernel patches | 23:45 |
| lkcl | i haven't heard from ben for some months | 23:46 |
| segher | i don't see him much either... last week on irc though :-) | 23:46 |
| segher | (but i just saw he was there... time zones) | 23:46 |
| lkcl | i'm in the UK yet have.. ahh... "adjusted" to waking up somewhere around 12 / 1pm... :) | 23:48 |
| lkcl | my excuse is, "so i can talk to people in the US". of course, when i visit the US or Canada the exact same thing happens lol | 23:49 |
| segher | i usually have my alarm at 10am... i'm in .nl, but work US time mostly | 23:49 |
| segher | i often woke up after noon, so i decided to stop doing that | 23:50 |
| lkcl | ah you're from the netherlands? i lived in scheveningen, den haag, for 4 years | 23:50 |
| lkcl | loved it | 23:50 |
| segher | i'll move to delft soon | 23:51 |
| segher | walking distance from the hague :-) | 23:51 |
| lkcl | i met this guy who used to cycle from rotterdam every day to den haag. holy s*** could he move. | 23:52 |
| lkcl | tried to keep up with him for 7 km... then he said, "ok bye" and added an extra 10km to his speed :) | 23:53 |
| segher | lol | 23:53 |
| segher | pretty dangerous, cycling fast there, usually | 23:53 |
| Kyrassier | Nur die Nacht ist edel und gut! Die beste Zeit zum Denken, nichts kann einen ablenken. (Only the night is noble and good. The best time to think, no distraction) | 23:53 |
| segher | the other traffic doesn't expect you | 23:53 |
| segher | kyrassier: genau :-) | 23:54 |
| lkcl | there's a dedicated cycle path that runs by the side of the freeway, now, from den haag to rotterdam | 23:54 |
| segher | yes, but there are cyclists on it | 23:54 |
| lkcl | haha yes | 23:54 |
| Kyrassier | how fast could he move? | 23:55 |
| Kyrassier | km/h? | 23:55 |
| segher | 30 or a bit more, i'd guess | 23:55 |
| Kyrassier | lol :) | 23:55 |
| Kyrassier | depends on the headwind, though | 23:55 |
| segher | that is easy in .nl | 23:56 |
| lkcl | about 40km/h!! | 23:56 |
| segher | you *always* have headwind | 23:56 |
| segher | and if you turn around, you still do | 23:56 |
| Kyrassier | yah. i remember | 23:56 |
| lkcl | i was able to do around 25 km/h sustained, i was pushing myself to 30 km/h to impress him | 23:56 |
| segher | 30 is quite doable with a good bik | 23:56 |
| segher | bike | 23:56 |
| lkcl | yes, he had wheels only 18mm profile (!) | 23:57 |
| * Kyrassier could do 73 peak for maybe 2 minutes, 60 to 65 on flat grounds for about an hour, and always 50 to 55. oh err, and 45 at 12% uphill, | 23:58 | |
| segher | lkcl: wow, most are about 25mm | 23:58 |
| lkcl | wha-how! | 23:58 |
| lkcl | i bought a Richards S8 from a shop in den haag, it's a semi-custom MTB | 23:59 |
| Kyrassier | nowadays i do 30 to 35 on an old 3-speed without sweat, and if i really push it maybe 45 | 23:59 |
| segher | 18 is really tiny... i wonder what pressure that is | 23:59 |
| lkcl | i felt safer with MTB slicks and with good brakes | 23:59 |
| lkcl | 100 psi | 23:59 |
| segher | and that is? in real-world units | 23:59 |
| lkcl | 90 to 100 psi is normal for racers | 23:59 |
| segher | less than 7atm | 23:59 |
| segher | that is low | 23:59 |
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