| Chips4Makers | Am close to commiting first cocotb setup for testing with iverilog. Did notice though iverilog 11.0 doesn't like the empty mem init files; it wants a file with the right number of words. Debian currently has v10.3 and that just gives a warning. | 10:47 |
|---|---|---|
| lkcl | Chips4Makers, excellent! already! | 10:54 |
| lkcl | ahh... you're using iverilog? on the mem.init files? why? | 10:55 |
| lkcl | we already have pre-simulation running from verilator, using litex. | 10:56 |
| lkcl | i guess, it's nice to use cocotb for both. | 10:56 |
| * lkcl just checked with litex | 10:56 | |
| lkcl | yes, litex does build a mem.init with the exact size | 10:57 |
| lkcl | even if it is full mostly of zeros | 10:57 |
| Chips4Makers | lkcl: I want to use exact same cocotb tb on pre-layout and post-layout netlist. | 10:59 |
| Chips4Makers | As said verilator version from debian is too old for cocotb and I had problems compiling newer version. I am now first going to focus on post-layer simulation and just leave pre-layout with iverilog. | 11:01 |
| Chips4Makers | post-layer -> post-layout | 11:01 |
| Chips4Makers | Also, in general I try to avoid litex stuff as much as possible... | 11:03 |
| Chips4Makers | And the loops I needed to get through to get the setup working has only confirmed this believe. | 11:05 |
| Chips4Makers | lkcl: So which step should generate the mem init files ? | 11:07 |
| lkcl | ahh ok. | 12:06 |
| lkcl | yes good idea about skipping litex :) | 12:06 |
| lkcl | Chips4Makers: make ls180 | 12:06 |
| lkcl | however they are all entirely empty | 12:06 |
| lkcl | you could fill them with zeros (of the right length) | 12:06 |
| Chips4Makers | make ls180 still tries to copy mem_2.init | 12:19 |
| Chips4Makers | lkcl: Which repo URL do I need to use to have write access ? | 12:30 |
| Chips4Makers | lkcl: found it | 12:34 |
| Chips4Makers | lkcl: Don't seem to have write access to libresoc-litex; can fetch through ssh but not push. | 12:40 |
| lkcl | Chips4Makers, 1 sec will sort that out | 12:45 |
| lkcl | done | 12:46 |
| lkcl | Chips4Makers: ah yeah i dropped the options (number of srams) down to 2, from the previous 5 | 12:46 |
| lkcl | s/srams/DFF srams/ | 12:47 |
| lkcl | and forgot to comment out the cp of mem*.inits not created | 12:47 |
| lkcl | Jean-Paul sent me some code yesterday which does ghdl-based simulation | 12:50 |
| lkcl | it contains info / advice how to parse / fix the vst files so they compile with ghdl | 12:50 |
| lkcl | cocotb page says "it's possible" (to use ghdl), lots of people saying (dating back 2-5 years) "can't" | 12:52 |
| Chips4Makers | lkcl: Also write for soc.git | 12:54 |
| lkcl | eh? doh | 12:55 |
| Chips4Makers | lkcl: I have used ghdl from cocotb in the past. | 12:55 |
| lkcl | done | 12:55 |
| lkcl | excellent | 12:55 |
| Chips4Makers | I was own compiled ghdl though. ghdl only releases version once a year and then distros may even run more behind. | 12:56 |
| lkcl | yehyeh, i think i have the same | 12:56 |
| lkcl | it was a pig, i remember that :) | 12:57 |
| lkcl | finding a version that worked with microwatt | 12:57 |
| lkcl | ghdl --version | 12:57 |
| lkcl | GHDL 1.0-dev (v0.37.0-819-g9828b513) [Dunoon edition] | 12:57 |
| lkcl | i ran the cocotb test, it's got iverilog build errors, i take it you've managed to work those out? | 12:58 |
| lkcl | did you get "clk_sel_i is not a port of test_issuer"? | 12:59 |
| * lkcl investigating | 13:01 | |
| Chips4Makers | What iverilog version ? I have 10.3 in Linux Mint. | 13:05 |
| lkcl | iverilog -v | 13:06 |
| lkcl | Icarus Verilog version 11.0 (devel) (s20150603-519-g585a023) | 13:06 |
| lkcl | i must have built it from source. it's complaining of missing ports (which aren't used, but hey) | 13:06 |
| lkcl | ahh i know what's going on | 13:08 |
| Chips4Makers | lkcl: also just pushed new version of idcode.svf | 13:11 |
| lkcl | Chips4Makers, star | 13:11 |
| lkcl | ../libresoc.v:199380: syntax error | 13:11 |
| lkcl | Segmentation fault | 13:11 |
| lkcl | *snort* :) | 13:11 |
| lkcl | casez (1'h0) | 13:12 |
| lkcl | endcase | 13:12 |
| lkcl | ???? | 13:12 |
| lkcl | i know why that is - it's an optimised-out constant | 13:14 |
| lkcl | hopefully there aren't any more of those | 13:16 |
| lkcl | okaaaay | 13:21 |
| lkcl | underway | 13:21 |
| lkcl | modgrammar.ParseError: [line 1, column 1] Expected '!' or 'ENDDR' or 'ENDIR' or 'RUNTEST' or 'SDR' or 'SIR' or 'STATE' or 'TRST' or end of line: Found 'HIR 5 TDI (1f) S' | 13:22 |
| lkcl | what's that about? :) | 13:22 |
| lkcl | pip3 install modgrammar | 13:23 |
| lkcl | Collecting modgrammar | 13:23 |
| lkcl | Downloading modgrammar-0.10.tar.gz | 13:23 |
| lkcl | Chips4Makers, i disabled pll for now. | 13:24 |
| lkcl | iverilog builds and cocotb runs! w00t! | 13:24 |
| * lkcl wonders if i have to update cocotb, i think i did recently | 13:27 | |
| Chips4Makers | I did not make modgrammar dependency of c4m-jtag as it is only needed when using cocotb jtag support. From the other side it is not that big. | 13:28 |
| Chips4Makers | A little smoother than litex :) | 13:29 |
| lkcl | File "/home/lkcl/src/libresoc/c4m-jtag/c4m/cocotb/jtag/c4m_jtag_svfcocotb.py", line 228, in run | 13:31 |
| lkcl | yield self.execute(p.parse_string(cmds)) | 13:31 |
| lkcl | which is then expecting modgrammar | 13:31 |
| lkcl | lol yes | 13:31 |
| lkcl | did you happen to update c4m-jtag? | 13:32 |
| lkcl | this resonates https://gitlab.com/Chips4Makers/c4m-jtag/-/commit/cfde460838dffbd5005fd6fbdc9059266e5126d2 | 13:33 |
| lkcl | yes i have the same commit https://gitlab.com/Chips4Makers/c4m-jtag/-/commit/cfde460838dffbd5005fd6fbdc9059266e5126d2 | 13:34 |
| lkcl | Chips4Makers, any ideas? https://ftp.libre-soc.org/iverilog_cocotb.txt | 13:39 |
| lkcl | biab, walk. | 13:39 |
| Chips4Makers | SVF support in c4m-jtag is incomplete so that's why I made specific .svf for test. Am first going to focus on post-layout simulation. | 13:46 |
| Chips4Makers | BTW, did push to c4m-jtag on libresoc. | 13:47 |
| lkcl | ahh ok | 14:30 |
| lkcl | great | 14:30 |
| lkcl | Chips4Makers: i've started some experimentation here https://git.libre-soc.org/?p=soc-cocotb-sim.git;a=tree;f=ls180;hb=HEAD | 14:30 |
| lkcl | from Jean-Paul's work he sent me, problems are "fixed" in the coriolis2 vst files by replacing "linkage vss" with "in vss" | 14:31 |
| lkcl | i am just going to do an experiment and write a python script which batch-processes an entire directory to do that | 14:32 |
| lkcl | Chips4Makers, there's two errors. firstly double-underscores (this comes from ilang files) | 14:40 |
| lkcl | secondly, the keyword "linkage" | 14:40 |
| Chips4Makers | lkcl: OK, maybe I can then focus on .svf that does boundary scan ? | 14:40 |
| lkcl | sorted | 14:40 |
| lkcl | https://git.libre-soc.org/?p=soc-cocotb-sim.git;a=tree;f=ls180;hb=HEAD | 14:40 |
| lkcl | yes good idea | 14:40 |
| Chips4Makers | ghdl is quite strict in default configuration but should have option to be more permissive. Did you try that ? | 14:41 |
| lkcl | i will let you know when i have something that will need your experience having done the cocotb-vhdl before | 14:41 |
| lkcl | ahh no :) | 14:41 |
| lkcl | how's that work? | 14:42 |
| lkcl | ghdl --help is terribly short on detail :) | 14:42 |
| lkcl | ghdl --options-help looks promising | 14:42 |
| lkcl | ahh probably --relaxed-rules | 14:43 |
| Chips4Makers | that what I was aiming at | 14:44 |
| lkcl | ok apparently it's for checking not compiling | 14:48 |
| lkcl | urrr there are outputs that get used as inputs. i'm using experiment10 as a quick test | 14:56 |
| lkcl | https://git.libre-soc.org/?p=soclayout.git;a=blob;f=experiments10/add.py;hb=HEAD | 14:57 |
| lkcl | example: posjtag_rst is an output as declared by the C4M-JTAG FSM module | 14:57 |
| lkcl | buuut | 14:57 |
| lkcl | it is used as an *input* into some circuits such as deciding what to do with tms | 14:58 |
| lkcl | will try different standard versions | 15:00 |
| lkcl | ha! --std=08 does the trick | 15:00 |
| lkcl | ok, getting somewhere. i have a successful build using experiments10 VST files | 15:15 |
| lkcl | from corona.vst (and everything it needs) | 15:15 |
| lkcl | okaaay found this https://gitlab.com/Chips4Makers/c4m-jtag/-/blob/master/test/vhdl/cocotb/dual_parallel/Makefile | 15:18 |
| Chips4Makers | Running ghdl from cocotb should be with SIM=ghdl and defining VHDL_SOURCES. docker container ghdl/cosim:vunit-cocotb should show an environment with working cocotb+ghdl setup. | 15:23 |
| Chips4Makers | My local setup does currently not work, likely because I upgraded ghdl. | 15:23 |
| lkcl | aiyaa | 15:26 |
| lkcl | Chips4Makers: ha! actually generated a test.ghw and it looks "sane" | 15:46 |
| lkcl | if you'd like to give that a shot the vst source for experiment10 is here https://ftp.libre-soc.org/t2.tgz | 15:48 |
| * lkcl need to get up and walk about again :) | 15:48 | |
| lkcl | must do README | 15:48 |
| Chips4Makers | lkcl: Where do I find the order of pins added to boundary scan ? | 16:13 |
| Chips4Makers | OK, found it in __init__ of class LibreSoC. | 16:15 |
| lkcl | run "make mkpinmux" | 16:38 |
| lkcl | 1 sec... | 16:38 |
| lkcl | Chips4Makers: it's created automatically through the class Pins https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/jtag.py;hb=HEAD#l36 | 16:42 |
| * lkcl tracking that through, 1 sec | 16:42 | |
| lkcl | i just realised the order can change because the pinmux program generates non-ordered dictionaries | 16:42 |
| lkcl | Chips4Makers: the purpose of the Pinmux is to auto-generate an ordered pinset precisely so that it is unnecessary to manually type out hundreds of pins | 16:51 |
| lkcl | which could change | 16:51 |
| lkcl | Chips4Makers, experiments10 ghdl cocotb passes the first unit test (IDCODE)! | 17:02 |
| lkcl | fails on the reset one but hey | 17:02 |
| lkcl | HA! got it to work | 17:35 |
| lkcl | Chips4Makers, using ls180_pins.py for the pin-definitions is quite important, it is a straight dictionary but now an OrderedDict | 17:36 |
| lkcl | there was the possibility, previously, of pin order being completely mixed | 17:36 |
| Chips4Makers | lkcl: Actually best order in scan chain is clockwise or counter clockwise as they are in the IO ring starting from the JTAG pins. This way the boundary scan shift register can naturally follow the IOs. Not critical for this tape-out. | 19:00 |
| Chips4Makers | Nice about ghdl + cocotb | 19:00 |
| Chips4Makers | Boundary scan does not work for the moment. Debugging is for tomorrow. | 19:01 |
| lkcl | Chips4Makers: yeah :) | 19:35 |
| lkcl | rest. | 19:35 |
| lkcl | i may move things about (later tonight), | 19:35 |
| lkcl | unless you tell me that you've work not-yet-committed | 19:36 |
| Chips4Makers | NP, I should be able to adapt. | 19:36 |
| programmerjake | https://www.rfc-editor.org/rfc/rfc8962.html | 19:40 |
| programmerjake | XD | 19:41 |
| lkcl | programmerjake: lol | 22:24 |
| lkcl | Chips4Makers, all done, you'll need: | 23:43 |
| lkcl | make gitupdate mkpinmux ls180_verilog_nopll | 23:44 |
| lkcl | tomorrow. that should do it | 23:44 |
| lkcl | confirmed that run_iverilog_sim.sh still passes | 23:45 |
| lkcl | now here as a submodule lkcl@fizzy:~/src/libresoc/soc/src/soc/soc-cocotb-sim/ls180/pre_pnr | 23:45 |
Generated by irclog2html.py 2.17.1 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!