Monday, 2021-04-05

lkclChips4Makers, appreciated the heads-up there. i read a JTAG spec and wondered about the VHDL. that was before i could read VHDL easily though :)11:01
* lkcl taking a look at the sdram_dq_oe this morning11:39
lkclChips4Makers: sorted12:06
lkcl ./ passes12:06
Chips4Makerslkcl: hooray12:20
lkclyeah :)12:56
Chips4Makerslkcl: Where did the DMI come from ? I don't anything online on this implementation. I only find direct media interface and differential memory interface.13:42
Chips4MakersI'm not convinced to upstream it. It would seem straight forward to implement a (zero waitstate) WB2DMI bridge in nmigen-soc and only keep Wishbone master in JTAG.13:42
lkclChips4Makers, it's a standard interface, named "Debug Module Interface"14:55
lkclit's as ubiquitous and general-purpose as Wishbone - just not very well-known14:59
Chips4MakersSo you implemented the registers in libre-soc as specified by the standard ? Then it makes sense to upstream, maybe with having the register bank included.15:59
lkclChips4Makers: for RISC-V there exists a DMI standard.  and for other processors as well16:01
lkclsorry: the DMI standard *is* a standard16:02
lkclfor RISC-V, there exists a defined set of DMI addresses, as specified by the RISC-V Foundation Debug Working Group16:02
lkclin the case of OpenPOWER, nobody has done that job16:02
lkcltherefore, Microwatt defined their own: we copied them.16:02
lkcltherefore, those DMI addresses also effectively become a standard16:03
lkclhowever, none of these DMI address register standards have anything to do with the fact that DMI *itself* is a recognised industry standard, just like Wishbone.16:03
Chips4MakersWas asking because the document you linked defined the widith of the address of the DMI interface.16:04
lkclwhich is defined exactly as Wishbone address is defined... or not defined16:05
lkclthe equivalence between DMI standard and Wishbone standard is one-to-one16:05
lkclas in: neither the DMI standard nor the Wishbone standard *demand* a specific address width.16:05
lkcl... but that is not a reason to say "wishbone should be removed from C4M-JTAG because the Wishbone address is not defined"16:05
Chips4MakersSo can you point me to a DMI document that says this ?16:06
lkclno, i can't, because i don't know where one is16:06
lkcli can take a look and see if one exists16:06
Chips4MakersSo it is not a standard in my opinion16:06
lkclit's implemented in Microsemi hardwar16:07
lkclSiFive products16:08
lkclit's a standard - nobody actually says or explains where they got it from.16:09
lkclit's just... a standard16:09
Chips4MakersOK, actually the spec does not define the physical bus interface (in section 3.1): "The Debug Module Interface can be a trivial bus withone master and one slave, or use a more full-featured bus like TileLink or the AMBA AdvancedPeripheral Bus.  The details are left to the system designer.". So Wishbone could also be used. I'm not saying the simple implementation doesn't make sense, just that I want to look further into thi16:15
lkclit's extremely basic: what you actually put *on* the DMI interface is entirely up to the implementor.16:20
lkcljust as with wishbone, what is put onto the wishbone bus (and at what width in terms of address and data) is also entirely and completely up to the implementor16:21
lkclif you hard-code *any* of those width parameters - simply because the RISC-V Sub-committee decided to define some particular choices16:21
lkclit would be as if you had said, "ah because wishbone product XYZ hard-codes Wishbone address @ 9 bits and data @ 8 bits, all other Wishbone addresses and data widths are PROHIBITED by C4M-JTAG"16:22
lkcljust as wishbone c4m-jtag is extremely simple, so is the dmi adaptation extremely simple.16:23
lkclit was literally a cut-and-paste16:23
lkclbecause the concepts are identical and equally general-purpose16:24
lkcli literally took the c4m-jtag "add_wishbone()" function and did a verbatim global search/replace "wishbone" --> "dmi"16:26
lkclDMI is effectively "a slightly simpler version of wishbone"16:27
lkclit's probably based on the SRAM interface.16:27
lkclthere's a "req" line, a "wen" line, address, and data in/out.16:28
lkclreq must be raised for only one cycle (just like wishbone)16:29
lkclthere must be 1 clock delay16:29
lkclthen "ack" must be asserted (with data)16:29
lkclit's *almost* identical to wishbone.16:29
Chips4MakersI disagree, have you actually read the 3.1 section (Debug Memory Interface) of the riscv-debug-spec ? It specifically does not discuss the physical implementation of the interface.16:34
Chips4MakersAnd it does specify that the address space has to start with a 32-bit register bank.16:35
lkclthat's the RISC-V implementor's decision16:57
lkclwe are talking at cross-purposes.16:57
lkclimagine this was wishbone that we were discussing to add16:57
lkclwhen you say "have you read the 3.1 secction of the riscv-debug spec" it is as if you had said, "have you read the Opencores I2C wishbone implementation source code"16:58
lkclor some other implementation.16:58
lkcli will try to track down a RISC-V JTAG-to-DMI adapter somewhere16:59
lkclto see if it is the same as the microwatt one16:59
Chips4MakersNo, riscv-debug-spec is the source definition of DMI, it is _the_ document that defines what DMI means. It is like the Wishbone Rev3 and Rev4 spec.17:01
lkclChips4Makers, that makes no sense, because Microwatt has also implemented DMI, and it has nothing to do with RISC-V17:04
* lkcl still investigating - you could well be right. i need to look further17:05
lkclariane uses SV so i need to track down where the type "dmi_req_t" and "dmi_resp_t" are defined17:05
lkclfound them17:10
lkclthat's defined as 6-bit DMI address and 32-bit DMI data17:11
lkclin microwatt17:11
lkclit's a 2-bit address and 64-bit data17:12
lkcl1 sec that's not correct17:12
lkclgive me a second, wrong file17:12
lkclthat's better.17:13
lkclthe microwatt team decided to go with a 4-bit DMI address and a 64-bit DMI data bus17:13
lkclriscv-debug-spec defines what widths the *RISC-V* DMI end-point chose to go with.17:14
lkclthey chose to go with a 6-bit DMI address and a 32-bit DMI data width17:14
lkclthis does not *define* that DMI *must* be 6-bit data and 32-bit addr17:15
lkclany more than choosing those widths would define that Wishbone must be those exact widths17:15
lkclunfortunately, i believe it is a standard that is in common use, and, clearly, the bus data/addr widths are general-purpose and arbitrary, but DMI is not common enough for someone to have actually written a document like the WB v3/4 spec17:17
lkclbit annoying17:17
Chips4MakersMaybe you could ask Microwatt guys on history of DMI interface ?17:21
lkclyeah good idea17:21
lkclit's easter at the moment and i think a lot of them are away on holiday17:22
lkclmight be a few weeks17:22

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