Tuesday, 2021-04-06

*** lx0 is now known as lxo00:26
programmerjakemy first pull request to Rust's standard library: https://github.com/rust-lang/rust/pull/8391708:18
lkclprogrammerjake, that's great - i do have to ask, how does it help the Libre-SOC Project?09:43
lkclis it something that is related to development of Kazan?09:43
programmerjakenot related to kazan in particular ... it's a general utility function that works with all iterators.10:03
programmerjakemostly just posted here cuz I wrote it and it's somewhat interesting10:04
lkclit's quite something to contribute to a big project. i had the same feeling working on samba10:28
lkclwe do however need more input from you on this project. we are extremely short on people and have limited time where NLnet PET grants will no longer be available (end of this year)10:29
programmerjakeyeah, sorry, keep getting distracted... virtual machines with llvm backends and all... :)10:35
programmerjakewell, ttyl, see you at the meeting! gotta get some sleep.10:39
cesar[m]1Is it allowed to load src/dst step with a value greater than or equal to VL? If so, the loop termination condition must be step >= VL, not just step == VL.11:48
lkclcesar[m]1, no it isn't allowed.  strictly speaking it should be an illegal instruction exception, treating this as a Sub-PC, it is as if executing something out of memory bounds12:08
cesar[m]1Got it.12:10
cesar[m]1I guess setting step=VL is allowed, it's the same as setting VL=0. It's setting step > VL which isn't allowed.12:49
cesar[m]1In fact, the vector instruction skip loop on Fetch could be VL==src/dst step, instead of just VL==0.12:50
cesar[m]1On the other hand, the "predicate mask skip zeros" step already checks for VL==step, and terminates the VL loop. So, we don't really need the VL==0 loop on Fetch anymore.12:59
lkclthe VL==0 test on fetch is there as a reminder that when we go to a pipelined design it can entirely skip that instruction13:27
lkclin pipelines all information is forward-progressing only13:31
lkclChips4Makers: urrrr cocotbext wishbone by wallento is out of date15:26
lkcland there's no "backwards compatibility support" in cocotb15:27
lkclcocotb.drivers has moved to a separate repo cocotb_bus15:27
Chips4Makerslkcl: I know changes that happened in cocotb but I was busy with something you may be able to guess :) This is for after tape-out.15:31
lkcli'd like to try testing the wishbone bus via cocotb15:35
lkclhowever now i just realised that cocotbext.wishbone is for co-simulating and it's not actually needed in the test i want to do15:36
lkclbecause the unit being tested *actually has* a wishbone memory in it15:37
Chips4Makerslkcl: Yeah, I think you should be able to initialize the memory with a program in it and then let the simulation run.15:57
Chips4MakersI looked myself and the only Wishbone cocotb test I could find is still using cocotbext.15:57
Chips4MakersYou can also use the JTAG as Wishbone master if what you want to test if accessible by a JTAG Wishbone master.15:58
lkcli realised, actually, yes: we aren't testing the wishbone capability of c4m-jtag15:59
lkclwe are simply sending JTAG commands, oh look! they happen to be ones that involve requesting from the black box called "libresoc.v" to return data over a wishbone bus15:59
lkclthe cocotbext.wishbone was for when there *is* no actual wishbone endpoint16:00
lkcland you need to simulate one (either wb slave or wb master)16:01
lkclwe *do* have one in libresoc.v16:01
lkclthe peripherals (UART at 0xc000800 or something like that)16:01
lkclDFF SRAM (at 0x00000 and 0x700)16:02
lkcletc. etc.16:02
lkclanyway: that's in.  it doesn't _work_ but it's in :)16:02
Chips4MakersYes, cocotbext wishbone is for unit testing subblocks.16:03
Chips4MakersIt would be nice though to be able connect some watchers that check if all signaling on the bus conforms to the WB spec.16:05
lkclyyeah good point16:07
lkcli need to take a look at the vcd output, see if it's at least functioning.16:09
lkclmight need to do DMI start/stop (stop the core, run "reset")16:10
lkcli did that here16:10
lkcljust not over JTAG - that was direct to DMI.16:11
lkclused it to enumerate (and print-dump) the entire register file16:11
Chips4Makerslkcl: I added support for prelayout cocotb sim on version with 4K SRAM blocks. I get several warnings of mismatched signals sizes in the verilog which seem suspicious.19:43
lkclChips4Makers: let me take a look21:06
lkclhow are those generated?21:09
lkclalso: on the testwb.py i'm getting a lock-up (of iverilog)21:10
lkclthe moment the wb ibus_sel is raised21:10
Chips4MakersWhat generated ? The VHDL/Verilog simulation models are now part of the c4m-flexmem code.21:11
lkcl./run_iverilog_ls180.sh is now joined by ./run_iverilog_wb_ls180.sh21:12
lkcli modified testwb.py to use dut.ls18021:12
lkcldut.ls180.test_issuer bypasses the pin pads21:13
lkcland may not be starting up the ls180.sys_clk properly21:13
lkclso i took a copy of test.py, called testwb.py21:14
lkcland modified it to connect to ls180.jtag_* and to ls180.sys_clk/rst21:14
lkclwhich means that it should be properly initialising the litex infrastructure, including the wishbone buses and peripherals21:15
Chips4MakersI do have /run_iverilog_wb_ls180.sh but I did not update it. I don't have testwb.py.21:22
Chips4MakersMy run of run_iverilog_ls180 with 4K SRAM version: https://nextcloud.stafverhaegen.be/index.php/s/rRGDJtEc5jEpYx221:32
Chips4MakersYou may need to run clean.sh to see warnings.21:32
lkclok great21:33
lkcli'm currently sorting out jtag_wb__sel21:33
Chips4MakersAlso iverilog may not be locked but just very slow. If you don't keep the CPU in reset the simulation is very slow. Would likely be good to get verilator also working.21:35
lkclahh ok21:35
lkclthat makes sense21:35
lkclahh forgot to add a granularity argument to TAP.add_wishbone21:37
Chips4MakersI did not add because you only read or write JTAG instruction. Thought was that people would add the master to an arbiter that would be able to handle the granularity conversion.21:44
Chips4Makers..you only have read or write JTAG instruction..21:44
lkclat 64-bit width.  makes sense21:52
lkcl(or... width-of-bus)21:52
lkclokaaaay now begins the fun of debugging vcd traces21:53
lkcli'm currently hand-patching ls180.v with this:21:53
lkclinitial begin21:53
lkcl       $dumpfile("ls180.vcd");21:53
lkcl       $dumpvars(0,ls180);21:53
lkcland it DoesTheJob(tm) under ivv21:53
lkclChips4Makers: jtag wb sel and SPBlock 4K SRAM we sorted22:07
programmerjakemeeting in few min: cesar  lxo  klys  Daniel Peterson  jn__22:58
programmerjakelkcl ^22:58
lkclprogrammerjake, thx23:01
lkclwe are on. cesar david cole23:02
lkclmaybe refresh if you are "sitting waiting"23:02
lxocalling in23:04
danielp3344did I miss the meeting?23:22
* danielp3344 only has 2 more days of this job, can hardly wait to do some stuff here23:23
cesar[m]1Daniel Peterson: The meeting is ongoing.23:24

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