| lkcl | Chips4Makers: very frustrating - enabling clock (run=True) causes a lock-up in both verilator *and* iverilog if allowed to run to the point where clock ticks not under reset | 14:32 |
|---|---|---|
| lkcl | however running under *litex* with verilator works perfectly well | 14:32 |
| lkcl | no lockup whatsoever | 14:32 |
| lkcl | however if i use verilator v4.106 there is *no* lockup | 14:35 |
| lkcl | however all output signals are zero | 14:35 |
| lkcl | all vcd trace signals are also zero | 14:35 |
| Chips4Makers | lkcl: OK, now I think of it, it may be because that the clock is defined in cocotb and not in verilog leading to a lot of round trips between python and iverilog. | 14:37 |
| lkcl | ahh ok | 14:48 |
| lkcl | so... that would involve writing a "manual" clock generator of some kind, in verilog? sys_clk = ~sys_clk or something? | 14:50 |
| lkcl | or a c++ module of some kind? | 14:51 |
| lkcl | in litex there is a module called "clocker", i will look it up | 14:51 |
| lkcl | https://github.com/enjoy-digital/litex/blob/master/litex/build/sim/core/modules/clocker/clocker.c | 14:55 |
| lkcl | is there an easy way in cocotb to run external clocks? | 14:58 |
| Chips4Makers | In Verilog/VHDL would be OK I think. | 15:15 |
| lkcl | Chips4Makers, https://gist.github.com/brabect1/9f8d7d144367b9f3dd77ba2a3b459f1d | 16:28 |
| lkcl | deep breath: it's going to need special modification of cocotb to be able to run a special thread that runs sys_clk independently | 16:29 |
| lkcl | https://gist.github.com/brabect1/9f8d7d144367b9f3dd77ba2a3b459f1d#file-xindep_clk-cpp-L137 | 16:29 |
| lkcl | which will require pthread mutexes around parts of cocotb/share/lib/verilator/verilator.cpp | 16:31 |
| Chips4Makers | Can't you just hack in verilog code in top level ? | 16:37 |
| lkcl | Chips4Makers, using which signal to drive the clock? | 16:40 |
| lkcl | there has to be a clock... to drive the clock | 16:40 |
| Chips4Makers | I'm not sure about verilog, you should be able to use #n to execute something after a certain amount of time. In VHDL it would be 'clk <= ~clk after 10ns;' | 16:43 |
| Chips4Makers | https://stackoverflow.com/questions/24924956/verilog-testbench-clock | 16:45 |
| lkcl | ahh yeah that would do it | 17:01 |
| lkcl | verilator: always #xxx is unsupported | 17:15 |
| lkcl | i'm tempted to suggest using cxxsim. | 17:17 |
| lkcl | it can do mixed VHDL, verilog and ilang, | 17:18 |
| lkcl | https://tomverbeure.github.io/2020/11/04/VHDL_Verilog_Cosimulation_with_CXXRTL.html | 17:18 |
| lkcl | it's not really cosimulation because it's just "converting everything to c++" | 17:18 |
| lkcl | and i already have some JTAG test benches (assuming a general JTAG interface) | 17:22 |
| lkcl | https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/test/test_jtag_tap.py;hb=HEAD | 17:22 |
| Chips4Makers | cxxsim is mainly WIP and can't be used from cocotb AFAIK. | 18:54 |
| Chips4Makers | Most of the questions on nmigen channel are answered by whitequark that it is a feature planned for the future... | 18:56 |
| lkcl | Chips4Makers, yes i took a look again at it - i thought there'd been much more progress | 20:25 |
| lkcl | meeting 20mins lxo programmerjake cesar[m]1 | 21:39 |
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