Wednesday, 2021-04-07

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lkclChips4Makers: very frustrating - enabling clock (run=True) causes a lock-up in both verilator *and* iverilog if allowed to run to the point where clock ticks not under reset14:32
lkclhowever running under *litex* with verilator works perfectly well14:32
lkclno lockup whatsoever14:32
lkclhowever if i use verilator v4.106 there is *no* lockup14:35
lkclhowever all output signals are zero14:35
lkclall vcd trace signals are also zero14:35
Chips4Makerslkcl: OK, now I think of it, it may be because that the clock is defined in cocotb and not in verilog leading to a lot of round trips between python and iverilog.14:37
lkclahh ok14:48
lkclso... that would involve writing a "manual" clock generator of some kind, in verilog?  sys_clk = ~sys_clk or something?14:50
lkclor a c++ module of some kind?14:51
lkclin litex there is a module called "clocker", i will look it up14:51
lkclhttps://github.com/enjoy-digital/litex/blob/master/litex/build/sim/core/modules/clocker/clocker.c14:55
lkclis there an easy way in cocotb to run external clocks?14:58
Chips4MakersIn Verilog/VHDL would be OK I think.15:15
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lkclChips4Makers, https://gist.github.com/brabect1/9f8d7d144367b9f3dd77ba2a3b459f1d16:28
lkcldeep breath: it's going to need special modification of cocotb to be able to run a special thread that runs sys_clk independently16:29
lkclhttps://gist.github.com/brabect1/9f8d7d144367b9f3dd77ba2a3b459f1d#file-xindep_clk-cpp-L13716:29
lkclwhich will require pthread mutexes around parts of cocotb/share/lib/verilator/verilator.cpp16:31
Chips4MakersCan't you just hack in verilog code in top level ?16:37
lkclChips4Makers, using which signal to drive the clock?16:40
lkclthere has to be a clock... to drive the clock16:40
Chips4MakersI'm not sure about verilog, you should be able to use #n to execute something after a certain amount of time. In VHDL it would be 'clk <= ~clk after 10ns;'16:43
Chips4Makershttps://stackoverflow.com/questions/24924956/verilog-testbench-clock16:45
lkclahh yeah that would do it17:01
lkclverilator: always #xxx is unsupported17:15
lkcli'm tempted to suggest using cxxsim.17:17
lkclit can do mixed VHDL, verilog and ilang,17:18
lkclhttps://tomverbeure.github.io/2020/11/04/VHDL_Verilog_Cosimulation_with_CXXRTL.html17:18
lkclit's not really cosimulation because it's just "converting everything to c++"17:18
lkcland i already have some JTAG test benches (assuming a general JTAG interface)17:22
lkclhttps://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/test/test_jtag_tap.py;hb=HEAD17:22
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Chips4Makerscxxsim is mainly WIP and can't be used from cocotb AFAIK.18:54
Chips4MakersMost of the questions on nmigen channel are answered by whitequark that it is a feature planned for the future...18:56
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lkclChips4Makers, yes i took a look again at it - i thought there'd been much more progress20:25
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lkclmeeting 20mins lxo programmerjake cesar[m]121:39
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