| Chips4Makers | lkcl: Should I be able to copy ls180.il from litex/florent to soclayout/experiments9 and run make there ? | 08:31 |
|---|---|---|
| Chips4Makers | I get following error: hurricane.HurricaneError: [ERROR] No .model or cell named <$mem> has been found. | 08:31 |
| lkcl | sigh: only with a version of yosys up to Yosys 0.9+4008 (git sha1 049e3abf9, | 10:27 |
| lkcl | not after that point | 10:27 |
| lkcl | Chips4Makers: long story | 10:27 |
| lkcl | if you check in the git revision history, that was the point where they changed... | 10:29 |
| lkcl | ok, hold on to your hat: | 10:29 |
| lkcl | yosys changed over from $mem to $memwr ports some time in december | 10:30 |
| lkcl | however they *also* fixed some bugs but those were fixed *later*, and the two bugsets overlap | 10:30 |
| lkcl | so | 10:30 |
| lkcl | deep breath | 10:30 |
| lkcl | you have to *litex compile* with this version: Yosys 0.9+3981 (git sha1 a3528649, | 10:31 |
| lkcl | then in the coriolis2 chroot compile with *this* version: Yosys 0.9+4008 (git sha1 049e3abf9, | 10:31 |
| lkcl | i know - it's awful. it's what i could find that "worked" | 10:31 |
| lkcl | this is temporary, whilst the manual layout is relying on looking for "$mem" | 10:52 |
| lkcl | if we want to try switching to latest-master-yosys it has to be coordinated with Jean-Paul, who has to redesign the P&R to use $memrd and $memwr ports | 10:53 |
| lkcl | this would be really good to raise a bugreport with yosys that the older $mem really needs to stay in as a compile-time option. | 10:53 |
| lkcl | https://github.com/YosysHQ/yosys/commit/a3528649 | 10:56 |
| lkcl | it works! https://git.libre-soc.org/?p=soc-cxxrtl-sim.git;a=tree;f=small_jtag_test;hb=HEAD | 14:45 |
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