| lkcl | Chips4Makers: successfully managed to upload a short loop and execute it on the cxxrtl simulation | 10:21 |
|---|---|---|
| lkcl | https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/firmware_upload.py;hb=HEAD | 10:21 |
| Chips4Makers | lkcl: If you could provide a short program that changes GPIO like blinking or so, that would be easy to do as test on real chip. | 10:30 |
| lkcl | Chips4Makers, yeah that's a good one. have to fit it into a ridiculously small number of instructions though | 10:35 |
| programmerjake | well, how's this for small instruction count: https://gcc.godbolt.org/z/PYMcKTWcM | 11:15 |
| programmerjake | just replace constants with real values and you have blinky lights! | 11:16 |
| programmerjake | ^ Ch ips4Makers lkcl | 11:16 |
| programmerjake | 8 instructions! | 11:18 |
| lkcl | programmerjake: ooOoo :) | 12:37 |
| lkcl | hey neat, using CTR | 12:37 |
| lkcl | ahh yeah, creating 32-bit offsets from immediates, requires 5 instructions *sigh* | 12:39 |
| lkcl | Chips4Makers, any day meeting (preferably afternoon) is good for me | 13:51 |
| lkcl | Chips4Makers: i upgraded to the latest ghdl (to fix a missing IEEE function in yosys ghdl plugin) | 14:28 |
| lkcl | i'm now getting "multiple assignments for "sff_m" offsets 0:0" | 14:29 |
| lkcl | in sff1r_x4.vhdl | 14:29 |
| lkcl | (after conversion from vbe to vhdl) | 14:29 |
| lkcl | any clues | 14:29 |
| lkcl | ? | 14:29 |
| lkcl | https://ftp.libre-soc.org/sff1r_x4.vhd | 14:30 |
| lkcl | https://gitter.im/ghdl1/Lobby?at=5ebdde145dcf0263d4e62c53 | 14:31 |
| Chips4Makers | I don't think you may assign a signal in two different processes. | 14:42 |
| Chips4Makers | Anyway I don't use vbe files anymore. Maybe you can use the vhd model of the PDKMaster FreePDK45 release ? | 14:42 |
| lkcl | Chips4Makers: ahh good idea | 14:46 |
| Chips4Makers | lkcl: I don't know though if I have tested the VHDL, it can be that I tested the Verilog model. | 14:49 |
| lkcl | as long as i've got something. vhdl would be better | 14:50 |
| lkcl | where are the cells? | 14:50 |
| Chips4Makers | The models are part of the release file: https://gitlab.com/Chips4Makers/c4m-pdk-freepdk45/-/releases | 14:51 |
| Chips4Makers | in views/FreePDK45/FlexLib/vhdl directory of tarball. | 14:52 |
| lkcl | getting there.... | 14:52 |
| lkcl | whewww took a while | 14:53 |
| lkcl | ngggggh nsxlib/sff1r_x4.vhd:48:1:error: latch infered for net "sff_m" | 14:56 |
| lkcl | frickin 'ell :) | 14:58 |
| lkcl | https://github.com/ghdl/ghdl/issues/938 | 14:58 |
| lkcl | rrrright. | 15:00 |
| lkcl | ok | 15:00 |
| * lkcl exasperated :) | 15:00 | |
| lkcl | it might be possible to use the verilog freepdk45 library cells instead | 15:00 |
| lkcl | one thing after another :) | 15:01 |
| Chips4Makers | I think you can easily fix the converted vbe file: https://nextcloud.stafverhaegen.be/index.php/s/wKFPgew5ggpgM4A | 15:10 |
| Chips4Makers | This analyzes and elaborates. | 15:10 |
| lkcl | ahh good, you know what you're doing. i don't :) | 15:19 |
| lkcl | retrospectively i can see what you did | 15:19 |
| lkcl | HA! | 15:23 |
| lkcl | excellent! | 15:23 |
| lkcl | basic test (add.py) actually damn well works | 15:24 |
| lkcl | that's pre-layout | 15:24 |
| lkcl | i.e. after blif2vst extraction | 15:24 |
| lkcl | gaaaah | 15:24 |
| lkcl | Chips4Makers, thank you for that correct vhd file, it worked | 15:28 |
Generated by irclog2html.py 2.17.1 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!