| lkcl | cesar[m]1: excellent | 01:12 |
|---|---|---|
| lkcl | btw "new_dstmask.eq(1<<shift)" would be more efficient / effective than bit_select(x,1).eq(1) | 01:13 |
| lkcl | using bit_select() as an assignment expression creates a ton of extraneous gates | 01:14 |
| lkcl | also - you'll like this: srcstep can be set exactly to 1<<r3 :) | 01:14 |
| lkcl | no need to go through the process of skipping: if current srcstep < (1<<r3) then srcstep can be set *equal* to (1<<r3) | 01:16 |
| lkcl | CR predication is interesting, it's a little easier, in some ways, just read one CR at a time (per element operation) and use bit_select to get the one to test if it is equal to "inv" | 01:17 |
| cesar[m]1 | If we are zero mode, srcstep=1<<r3 is not right, we must operate on the zero mask bits as well. | 01:21 |
| cesar[m]1 | srcstep=r3, actually. | 01:21 |
| lkcl | err... err... ah! yes. i forgot about zero-mode. doh. | 01:22 |
| lkcl | yes, nonzeroing would have to be taken into consideration | 01:22 |
| Chips4Makers | lkcl: I pushed WIP of using C4M FreePDK45 for synthesis and P&R. soclayout/experiments9/freepdk_c4m45. I did not change anything yet in doDesign.py which was copied from tsmc_c018. `make vst` works, `make lvx` fails. | 17:05 |
| lkcl | Chips4Makers: fantastic | 17:07 |
| Chips4Makers | OK, will need to add VHDL/Verilog files for IO cells though. | 17:07 |
| lkcl | i switched to verilog btw | 17:07 |
| lkcl | this should in theory allow a more up-to-date yosys | 17:08 |
| lkcl | btw the names of the niolib cells clash with the names of the signals: iovss, iovdd, etc. | 17:08 |
| lkcl | one or the other will need to be changed | 17:09 |
| lkcl | in the soc-cocotb-sim i've renamed the entities to cmpt_iovdd (etc.) temporarily | 17:09 |
| Chips4Makers | Models done. | 17:15 |
| Chips4Makers | I don't do niolib, that you have arrange with JP. | 17:16 |
| lkcl | Chips4Makers, ahh ok | 18:02 |
| lkcl | Chips4Makers: ah i know what that is. i removed some of the litex peripherals, Jean-Paul created a "manual" pin layout (rather than use the auto-generated one that i specifically created so that mistakes like this don't happen) | 18:30 |
| lkcl | and it hasn't been updated | 18:30 |
| lkcl | i'll see if removing the hand-created (incorrect) ioPadsSpecs and replacing them with the auto-generated ones work | 18:35 |
| lkcl | Chips4Makers: it does | 18:38 |
| lkcl | however *sigh* i added in the version without the SPBlock_4ksram | 18:38 |
| lkcl | i need to rest. | 18:39 |
| lkcl | FreePDK45 build is underway now | 21:15 |
| lkcl | soclayout latest commit | 21:17 |
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