Monday, 2021-04-12

Chips4Makerslkcl: You seem to be using wrong branch of c4m-pdk-freepdk45. The master branch is the source branch without the coriolis files. The released-libresoc branch is the one with the release package files with some libresoc additions.09:44
Chips4Makerslkcl: I now get the following error for FreePDK45 when trying to do P&R: "Unable to find cell "cmpt_dec_auluuu", please check your <./coriolis2/>"10:04
Chips4MakersI assume this is because cmpt_dec_auluuu is defined in cmpt_dec_alu.vst10:04
lkclChips4Makers, you need to... ahh, i know what it is - use the patch here:10:42
* lkcl now has to find it... :)10:43
lkclJean-Paul is yet to commit that10:44
lkclChips4Makers, ok so i needed to know about the branch, otherwise git submodule update --init --remote will indeed pick up the wrong thing10:45
lkcl1 sec let me check how to (always) check out a particular branch10:46
Chips4MakersI added it in .gitmodules, you may need to update .git/config.10:46
lkclahh ok10:47
lkclgit submodules are a bit of a nuisance, there can be uneditable / unresolvable conflicts10:50
Chips4MakersI did not plan to support SRAM blocks for FreePDK45 for the current tape-out. I assume with the current setup you should be able to do pre- and post-layout simulations.10:51
lkclin theory it should be possible to drop in the SPBlock_4kSRAM.vhdl model10:53
lkcli ran the ghdl-cocotb post-layout yesterday overnight10:54
lkclit took about 12 hours to complete compilation, after manually hand-editing chip_r.vst and corona_cts_r.vst10:54
lkclonly to bomb out at runtime (after VPI loader) because corona_cts_r.vst had duplicate signal names covering all of the pad names10:55
lkclsignal sdram_dq_i_to_pad etc.10:56
lkcli should have run a small test first (adder) but i cannot get that up and running10:57
lkclneed Jean-Paul's help there10:57
Chips4MakersThe problem is that the layout of the SRAM cell is not available in FreePDK45 and I need to spend time on other things now.11:01
lkclChips4Makers: ah yehyeh ok so if added it wouldn't complete.  ok got it.11:03
Chips4Makerslkcl: Do you know that GHDL has three different back-ends ? mcode, gcc and llvm. Performance may differ between the back-ends.11:03
lkclahh and apparently llvm-9 is a lot quicker than anything else11:04
lkclChips4Makers, okaaay got the (quicker) experiments10_verilog operational11:57
lkclforgot to add "jtag_tck" in setCLOCK pattern-matching after renaming it to match ls180 pad names.11:57
lkcli've now got some *way* shorter turnaround test for *_cts.vst files.11:58
lkclmeeting's in 1 hour?11:58
lkclChips4Makers: got a "BigVia height too big" style error with experiments10_verilog on FreePDK4519:24
lkcltrying to change the chip size to see if it helps19:24
Chips4MakersBigVia is code from JP, can't help much there.19:40
lkclok thx23:28
lkcli'll comment out the error-check and carry on :)23:28
lkclahh it's to do with cfg.anabatic.routingGuage23:36

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