| Chips4Makers | lkcl: You seem to be using wrong branch of c4m-pdk-freepdk45. The master branch is the source branch without the coriolis files. The released-libresoc branch is the one with the release package files with some libresoc additions. | 09:44 |
|---|---|---|
| Chips4Makers | lkcl: I now get the following error for FreePDK45 when trying to do P&R: "Unable to find cell "cmpt_dec_auluuu", please check your <./coriolis2/settings.py>" | 10:04 |
| Chips4Makers | I assume this is because cmpt_dec_auluuu is defined in cmpt_dec_alu.vst | 10:04 |
| lkcl | Chips4Makers, you need to... ahh, i know what it is - use the patch here: | 10:42 |
| * lkcl now has to find it... :) | 10:43 | |
| lkcl | https://gitlab.lip6.fr/vlsi-eda/coriolis/-/issues/36 | 10:43 |
| lkcl | Jean-Paul is yet to commit that | 10:44 |
| lkcl | Chips4Makers, ok so i needed to know about the branch, otherwise git submodule update --init --remote will indeed pick up the wrong thing | 10:45 |
| lkcl | 1 sec let me check how to (always) check out a particular branch | 10:46 |
| Chips4Makers | I added it in .gitmodules, you may need to update .git/config. | 10:46 |
| lkcl | https://stackoverflow.com/questions/9189575/git-submodule-tracking-latest | 10:47 |
| lkcl | ahh ok | 10:47 |
| lkcl | git submodules are a bit of a nuisance, there can be uneditable / unresolvable conflicts | 10:50 |
| Chips4Makers | I did not plan to support SRAM blocks for FreePDK45 for the current tape-out. I assume with the current setup you should be able to do pre- and post-layout simulations. | 10:51 |
| lkcl | in theory it should be possible to drop in the SPBlock_4kSRAM.vhdl model | 10:53 |
| lkcl | i ran the ghdl-cocotb post-layout yesterday overnight | 10:54 |
| lkcl | it took about 12 hours to complete compilation, after manually hand-editing chip_r.vst and corona_cts_r.vst | 10:54 |
| lkcl | only to bomb out at runtime (after VPI loader) because corona_cts_r.vst had duplicate signal names covering all of the pad names | 10:55 |
| lkcl | signal sdram_dq_i_to_pad etc. | 10:56 |
| lkcl | i should have run a small test first (adder) but i cannot get that up and running | 10:57 |
| lkcl | need Jean-Paul's help there | 10:57 |
| Chips4Makers | The problem is that the layout of the SRAM cell is not available in FreePDK45 and I need to spend time on other things now. | 11:01 |
| lkcl | Chips4Makers: ah yehyeh ok so if added it wouldn't complete. ok got it. | 11:03 |
| Chips4Makers | lkcl: Do you know that GHDL has three different back-ends ? mcode, gcc and llvm. Performance may differ between the back-ends. | 11:03 |
| lkcl | ahh and apparently llvm-9 is a lot quicker than anything else | 11:04 |
| lkcl | Chips4Makers, okaaay got the (quicker) experiments10_verilog operational | 11:57 |
| lkcl | forgot to add "jtag_tck" in setCLOCK pattern-matching after renaming it to match ls180 pad names. | 11:57 |
| lkcl | i've now got some *way* shorter turnaround test for *_cts.vst files. | 11:58 |
| lkcl | meeting's in 1 hour? | 11:58 |
| Chips4Makers | Yes. | 12:05 |
| lkcl | ok | 12:35 |
| lkcl | ta | 12:35 |
| lkcl | Chips4Makers: got a "BigVia height too big" style error with experiments10_verilog on FreePDK45 | 19:24 |
| lkcl | trying to change the chip size to see if it helps | 19:24 |
| lkcl | https://ftp.libre-soc.org/nohup.out.bz2 | 19:33 |
| Chips4Makers | BigVia is code from JP, can't help much there. | 19:40 |
| lkcl | ok thx | 23:28 |
| lkcl | i'll comment out the error-check and carry on :) | 23:28 |
| lkcl | ahh it's to do with cfg.anabatic.routingGuage | 23:36 |
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